diff --git a/litex_boards/targets/digilent_cmod_a7.py b/litex_boards/targets/digilent_cmod_a7.py
index 3216e17..a9852e5 100755
--- a/litex_boards/targets/digilent_cmod_a7.py
+++ b/litex_boards/targets/digilent_cmod_a7.py
@@ -56,6 +56,7 @@ class AsyncSRAM(LiteXModule):
         data = issiram.data
         wen = issiram.wen
         cen = issiram.cen
+        oe = issiram.oe
         ########################
         tristate_data = TSTriple(data_width)
         self.specials += tristate_data.get_tristate(data)