From 4362cb23a18eb433c627f2ae72a8411e2e1f5f87 Mon Sep 17 00:00:00 2001 From: Bayi Date: Sat, 5 Aug 2023 19:56:32 +0200 Subject: [PATCH] Fix Digilent Cmod A7 ISSIRAM reading --- litex_boards/targets/digilent_cmod_a7.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex_boards/targets/digilent_cmod_a7.py b/litex_boards/targets/digilent_cmod_a7.py index 3216e17..a9852e5 100755 --- a/litex_boards/targets/digilent_cmod_a7.py +++ b/litex_boards/targets/digilent_cmod_a7.py @@ -56,6 +56,7 @@ class AsyncSRAM(LiteXModule): data = issiram.data wen = issiram.wen cen = issiram.cen + oe = issiram.oe ######################## tristate_data = TSTriple(data_width) self.specials += tristate_data.get_tristate(data)