From 43a1e13b5389c968f255f51823c97749ea275df9 Mon Sep 17 00:00:00 2001 From: Ilia Sergachev Date: Wed, 22 Dec 2021 03:13:30 +0100 Subject: [PATCH] zedboard: compress bitstream, derive default clk f --- litex_boards/platforms/digilent_zedboard.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/litex_boards/platforms/digilent_zedboard.py b/litex_boards/platforms/digilent_zedboard.py index 62493f0..c2738ad 100644 --- a/litex_boards/platforms/digilent_zedboard.py +++ b/litex_boards/platforms/digilent_zedboard.py @@ -206,6 +206,9 @@ class Platform(XilinxPlatform): def __init__(self): XilinxPlatform.__init__(self, "xc7z020clg484-1", _io, _connectors, toolchain="vivado") + self.toolchain.bitstream_commands = \ + ["set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", ] + self.default_clk_freq = 1e9 / self.default_clk_period def create_programmer(self): return OpenOCD(config="board/digilent_zedboard.cfg")