diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py
index 43769e9..bbde93e 100755
--- a/litex_boards/targets/acorn_cle_215.py
+++ b/litex_boards/targets/acorn_cle_215.py
@@ -87,7 +87,6 @@ class BaseSoC(SoCCore):
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform, sys_clk_freq)
-        self.add_csr("crg")
 
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py
index 9d5fe06..cc18085 100755
--- a/litex_boards/targets/aller.py
+++ b/litex_boards/targets/aller.py
@@ -70,7 +70,6 @@ class BaseSoC(SoCCore):
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform, sys_clk_freq)
-        self.add_csr("crg")
 
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py
index 366ad6c..30dc47a 100755
--- a/litex_boards/targets/nereid.py
+++ b/litex_boards/targets/nereid.py
@@ -67,7 +67,6 @@ class BaseSoC(SoCCore):
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform, sys_clk_freq)
-        self.add_csr("crg")
 
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py
index 96903e4..e716a85 100755
--- a/litex_boards/targets/tagus.py
+++ b/litex_boards/targets/tagus.py
@@ -70,7 +70,6 @@ class BaseSoC(SoCCore):
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform, sys_clk_freq)
-        self.add_csr("crg")
 
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size: