Merge pull request #577 from hansfbaier/qmtech-ddr3-fix
qmtech_artix7_fgg676/fbg484: fix wrong memory chip type
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commit
44ab802ae6
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@ -21,7 +21,7 @@ from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoVGAPHY
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from litex.soc.cores.video import VideoVGAPHY
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT41J128M16
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from litedram.modules import MT41K128M16
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from litedram.phy import s7ddrphy
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from litedram.phy import s7ddrphy
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from liteeth.phy.mii import LiteEthPHYMII
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from liteeth.phy.mii import LiteEthPHYMII
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@ -100,7 +100,7 @@ class BaseSoC(SoCCore):
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sys_clk_freq = sys_clk_freq)
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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self.add_sdram("sdram",
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phy = self.ddrphy,
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phy = self.ddrphy,
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module = MT41J128M16(sys_clk_freq, "1:4"),
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module = MT41K128M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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)
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@ -21,7 +21,7 @@ from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoVGAPHY
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from litex.soc.cores.video import VideoVGAPHY
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT41J128M16
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from litedram.modules import MT41K128M16
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from litedram.phy import s7ddrphy
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from litedram.phy import s7ddrphy
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from liteeth.phy.mii import LiteEthPHYMII
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from liteeth.phy.mii import LiteEthPHYMII
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@ -100,7 +100,7 @@ class BaseSoC(SoCCore):
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sys_clk_freq = sys_clk_freq)
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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self.add_sdram("sdram",
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phy = self.ddrphy,
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phy = self.ddrphy,
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module = MT41J128M16(sys_clk_freq, "1:4"),
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module = MT41K128M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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)
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