diff --git a/litex_boards/platforms/ulx3s.py b/litex_boards/platforms/ulx3s.py
index fc455b7..fb61618 100644
--- a/litex_boards/platforms/ulx3s.py
+++ b/litex_boards/platforms/ulx3s.py
@@ -81,6 +81,21 @@ _io_common = [
         IOStandard("LVCMOS33")
     ),
 
+    # SPIFlash
+    ("spiflash", 0,
+        Subsignal("cs_n", Pins("R2")),
+        Subsignal("miso", Pins("V2")),
+        Subsignal("mosi", Pins("W2")),
+        Subsignal("wp", Pins("Y2")),
+        Subsignal("hold", Pins("W1")),
+        IOStandard("LVCMOS33")
+    ),
+    ("spiflash4x", 0,
+        Subsignal("cs_n", Pins("R2")),
+        Subsignal("dq", Pins("W2", "V2", "Y2", "W1")),
+        IOStandard("LVCMOS33")
+    ),
+
     # OLED
     ("oled_spi", 0,
         Subsignal("clk",  Pins("P4")),
diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py
index 3f5811c..4053eb5 100755
--- a/litex_boards/targets/ulx3s.py
+++ b/litex_boards/targets/ulx3s.py
@@ -81,8 +81,10 @@ class _CRG(Module):
 
 class BaseSoC(SoCCore):
     def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis",
-        sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", sdram_rate="1:1", **kwargs):
+        sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", sdram_rate="1:1", spiflash=False, **kwargs):
         platform = ulx3s.Platform(device=device, revision=revision, toolchain=toolchain)
+        if spiflash:
+            self.mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq,
@@ -135,6 +137,8 @@ def main():
     parser.add_argument("--revision",        default="2.0",         help="Board revision: 2.0 (default) or 1.7")
     parser.add_argument("--sys-clk-freq",    default=50e6,          help="System clock frequency  (default: 50MHz)")
     parser.add_argument("--sdram-module",    default="MT48LC16M16", help="SDRAM module: MT48LC16M16 (default), AS4C32M16 or AS4C16M16")
+    parser.add_argument("--with-spiflash",   action="store_true",   help="Make the SPI Flash accessible from the SoC")
+    parser.add_argument("--flash-boot-adr",  type=lambda x: int(x,0), default=None, help="Flash boot address")
     parser.add_argument("--with-spi-sdcard", action="store_true",   help="Enable SPI-mode SDCard support")
     parser.add_argument("--with-sdcard",     action="store_true",   help="Enable SDCard support")
     parser.add_argument("--with-oled",       action="store_true",   help="Enable SDD1331 OLED support")
@@ -151,6 +155,7 @@ def main():
         sys_clk_freq     = int(float(args.sys_clk_freq)),
         sdram_module_cls = args.sdram_module,
         sdram_rate       = args.sdram_rate,
+        spiflash         = args.with_spiflash,
         **soc_sdram_argdict(args))
     assert not (args.with_spi_sdcard and args.with_sdcard)
     if args.with_spi_sdcard:
@@ -159,6 +164,10 @@ def main():
         soc.add_sdcard()
     if args.with_oled:
         soc.add_oled()
+    if args.with_spiflash:
+        soc.add_spi_flash(mode="1x", dummy_cycles=8)
+        if args.flash_boot_adr:
+            soc.add_constant("FLASH_BOOT_ADDRESS", args.flash_boot_adr)
 
     builder = Builder(soc, **builder_argdict(args))
     builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}