From 227296231573fcfa4059b5508d3799b6ef4f6a48 Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Mon, 15 Nov 2021 09:53:46 +0700 Subject: [PATCH 1/2] qmtech_10cl001: fix wrong sdram clock pin --- litex_boards/platforms/qmtech_10cl006.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/platforms/qmtech_10cl006.py b/litex_boards/platforms/qmtech_10cl006.py index 7a882df..8df772e 100644 --- a/litex_boards/platforms/qmtech_10cl006.py +++ b/litex_boards/platforms/qmtech_10cl006.py @@ -29,7 +29,7 @@ _io = [ ), # SDR SDRAM - ("sdram_clock", 0, Pins("Y6"), IOStandard("3.3-V LVTTL")), + ("sdram_clock", 0, Pins("P2"), IOStandard("3.3-V LVTTL")), ("sdram", 0, Subsignal("a", Pins( "R7 T7 R8 T8 R6 T5 R5 T4", From e16fa193fc281c31cfca379869d4f9cb7c64406f Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Mon, 15 Nov 2021 10:23:01 +0700 Subject: [PATCH 2/2] qmtech 10cl006: remove all options which won't fit into the device. use uartbone as default --- litex_boards/targets/qmtech_10cl006.py | 57 +++++--------------------- 1 file changed, 10 insertions(+), 47 deletions(-) diff --git a/litex_boards/targets/qmtech_10cl006.py b/litex_boards/targets/qmtech_10cl006.py index 92629da..1d89f3a 100755 --- a/litex_boards/targets/qmtech_10cl006.py +++ b/litex_boards/targets/qmtech_10cl006.py @@ -30,7 +30,7 @@ from liteeth.phy.mii import LiteEthPHYMII # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): - def __init__(self, platform, sys_clk_freq, with_ethernet, with_vga, sdram_rate="1:1"): + def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"): self.rst = Signal() self.clock_domains.cd_sys = ClockDomain() @@ -40,12 +40,6 @@ class _CRG(Module): else: self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) - if with_ethernet: - self.clock_domains.cd_eth = ClockDomain() - - if with_vga: - self.clock_domains.cd_vga = ClockDomain(reset_less=True) - # # # # Clk / Rst @@ -63,11 +57,6 @@ class _CRG(Module): else: pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) - if with_ethernet: - pll.create_clkout(self.cd_eth, 25e6) - if with_vga: - pll.create_clkout(self.cd_vga, 40e6) - # SDRAM clock sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk) @@ -81,6 +70,13 @@ class BaseSoC(SoCCore): ident_version=True, sdram_rate="1:1", **kwargs): platform = qmtech_10cl006.Platform(with_daughterboard=with_daughterboard) + # unfornunately not even SERV would fit the devices + kwargs["cpu_type"] = None + kwargs["integrated_sram_size"] = 0 + + # interact with the sdram with uartbone by default + kwargs["uart_name"] = "uartbone" + # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on QMTECH 10CL006" + (" + Daughterboard" if with_daughterboard else ""), @@ -89,8 +85,7 @@ class BaseSoC(SoCCore): # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, - sys_clk_freq, with_ethernet or with_etherbone, - with_video_terminal or with_video_framebuffer, + sys_clk_freq, sdram_rate=sdram_rate) # SDR SDRAM -------------------------------------------------------------------------------- @@ -103,24 +98,6 @@ class BaseSoC(SoCCore): l2_cache_size = kwargs.get("l2_size", 8192) ) - # Ethernet / Etherbone --------------------------------------------------------------------- - if with_ethernet or with_etherbone: - self.submodules.ethphy = LiteEthPHYMII( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth")) - if with_ethernet: - self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) - if with_etherbone: - self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) - - # Video ------------------------------------------------------------------------------------ - if with_video_terminal or with_video_framebuffer: - self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") - if with_video_terminal: - self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") - if with_video_framebuffer: - self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") - # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( @@ -134,21 +111,13 @@ def main(): parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") - parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default) or 1:2 Half Rate") + parser.add_argument("--sdram-rate", default="1:2", help="SDRAM Rate: 1:1 Full Rate (default) or 1:2 Half Rate") parser.add_argument("--with-daughterboard", action="store_true", help="Whether the core board is plugged into the QMTech daughterboard") - ethopts = parser.add_mutually_exclusive_group() - ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") - ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") - parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address") - parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting") sdopts = parser.add_mutually_exclusive_group() sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)") parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output") - viopts = parser.add_mutually_exclusive_group() - viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)") - viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA)") builder_args(parser) soc_core_args(parser) @@ -157,13 +126,7 @@ def main(): soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), with_daughterboard = args.with_daughterboard, - with_ethernet = args.with_ethernet, - with_etherbone = args.with_etherbone, - eth_ip = args.eth_ip, - eth_dynamic_ip = args.eth_dynamic_ip, ident_version = args.no_ident_version, - with_video_terminal = args.with_video_terminal, - with_video_framebuffer = args.with_video_framebuffer, with_spi_flash = args.with_spi_flash, sdram_rate = args.sdram_rate, **soc_core_argdict(args)