From 4604379f46bbb7e7bb4e00bace4760973d1f356e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 13 Sep 2024 09:45:24 +0200 Subject: [PATCH] platforms/sqrl_xcu1525: Revert previous commit, clk constraints were already present in DDR4 constraints. --- litex_boards/platforms/sqrl_xcu1525.py | 5 ----- 1 file changed, 5 deletions(-) diff --git a/litex_boards/platforms/sqrl_xcu1525.py b/litex_boards/platforms/sqrl_xcu1525.py index d67cd39..c414c9f 100644 --- a/litex_boards/platforms/sqrl_xcu1525.py +++ b/litex_boards/platforms/sqrl_xcu1525.py @@ -376,11 +376,6 @@ class Platform(XilinxUSPPlatform): def do_finalize(self, fragment): XilinxUSPPlatform.do_finalize(self, fragment) - # Clks Constraints. - self.add_period_constraint(self.lookup_request("clk300", 0, loose=True), 1e9/300e6) - self.add_period_constraint(self.lookup_request("clk300", 1, loose=True), 1e9/300e6) - self.add_period_constraint(self.lookup_request("clk300", 2, loose=True), 1e9/300e6) - self.add_period_constraint(self.lookup_request("clk300", 3, loose=True), 1e9/300e6) # For passively cooled boards, overheating is a significant risk if airflow isn't sufficient self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]")