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platforms/sqrl_xcu1525: Revert previous commit, clk constraints were already present in DDR4 constraints.

This commit is contained in:
Florent Kermarrec 2024-09-13 09:45:24 +02:00
parent 90ff3d1ea9
commit 4604379f46
1 changed files with 0 additions and 5 deletions
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litex_boards/platforms/sqrl_xcu1525.py
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@ -376,11 +376,6 @@ class Platform(XilinxUSPPlatform):
def do_finalize(self, fragment):
XilinxUSPPlatform.do_finalize(self, fragment)
# Clks Constraints.
self.add_period_constraint(self.lookup_request("clk300", 0, loose=True), 1e9/300e6)
self.add_period_constraint(self.lookup_request("clk300", 1, loose=True), 1e9/300e6)
self.add_period_constraint(self.lookup_request("clk300", 2, loose=True), 1e9/300e6)
self.add_period_constraint(self.lookup_request("clk300", 3, loose=True), 1e9/300e6)
# For passively cooled boards, overheating is a significant risk if airflow isn't sufficient
self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]")