From 467b14a0ad0e9d6f84f52288c2b24b913b88a165 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 9 Apr 2020 08:14:17 +0200 Subject: [PATCH] colorlight_5a_75b: minor comment changes. --- litex_boards/platforms/colorlight_5a_75b.py | 3 +-- litex_boards/targets/colorlight_5a_75b.py | 5 +++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/litex_boards/platforms/colorlight_5a_75b.py b/litex_boards/platforms/colorlight_5a_75b.py index 6564bd2..944338d 100644 --- a/litex_boards/platforms/colorlight_5a_75b.py +++ b/litex_boards/platforms/colorlight_5a_75b.py @@ -20,11 +20,10 @@ _io_v6_1 = [ # Documented by @smunaut ("user_btn_n", 0, Pins("R16"), IOStandard("LVCMOS33")), # serial + # There seems to be some capacitance on KEY+ pin, so high baudrates may not work (>9600bps). ("serial", 0, Subsignal("tx", Pins("U16")), # led (J19 DATA_LED-) Subsignal("rx", Pins("R16")), # btn (J19 KEY+) - # It seems there's some capacitance on the KEY+ pin, so bigger baudrates - # may not work IOStandard("LVCMOS33") ), diff --git a/litex_boards/targets/colorlight_5a_75b.py b/litex_boards/targets/colorlight_5a_75b.py index 131213c..1d77bb5 100755 --- a/litex_boards/targets/colorlight_5a_75b.py +++ b/litex_boards/targets/colorlight_5a_75b.py @@ -7,12 +7,13 @@ # # 1) SoC with regular UART and optional Ethernet connected to the CPU: # Connect a USB/UART to J19: TX of the FPGA is DATA_LED-, RX of the FPGA is KEY+. -# ./colorlight_5a_75b.py --uart-baudrate 9600 (add --with-ethernet to add Ethernet capability) +# ./colorlight_5a_75b.py --revision=7.0 (or 6.1) (--with-ethernet to add Ethernet capability) +# Note: on revision 6.1, add --uart-baudrate=9600 to lower the baudrate. # ./colorlight_5a_75b.py --load # You should see the LiteX BIOS and be able to interact with it. # # 2) SoC with UART in crossover mode over Etherbone: -# ./colorlight_5a_75b.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv +# ./colorlight_5a_75b.py --revision=7.0 (or 6.1) --uart-name=crossover --with-etherbone --csr-csv=csr.csv # ./colorlight_5a_75b.py --load # ping 192.168.1.50 # Get and install wishbone tool from: https://github.com/litex-hub/wishbone-utils/releases