diff --git a/litex_boards/platforms/pcbarts_klusterlab.py b/litex_boards/platforms/pcbarts_klusterlab.py index 4ecd9fe..02766b3 100644 --- a/litex_boards/platforms/pcbarts_klusterlab.py +++ b/litex_boards/platforms/pcbarts_klusterlab.py @@ -211,17 +211,15 @@ _io = [ # Subsignal("scl", Pins(""), IOStandard("LVCMOS33")), # Subsignal("sda", Pins(""), IOStandard("LVCMOS33")), Subsignal("cec", Pins("N26"), IOStandard("LVCMOS33")), - Subsignal("hdp", Pins("M26"), IOStandard("LVCMOS25")), + Subsignal("hdp", Pins("M26"), IOStandard("LVCMOS33")), ), # SFP0 - ("sfp_tx", 0, - Subsignal("p", Pins("P2")), - Subsignal("n", Pins("P1")) - ), - ("sfp_rx", 0, - Subsignal("p", Pins("R4")), - Subsignal("n", Pins("R3")) + ("sfp", 0, + Subsignal("txp", Pins("P2")), + Subsignal("txn", Pins("P1")), + Subsignal("rxp", Pins("R4")), + Subsignal("rxn", Pins("R3")) ), ("sfp_tx_disable_n", 0, Pins("R18"), IOStandard("LVCMOS33")), ("sfp_rx_los", 0, Pins("T19"), IOStandard("LVCMOS33")), @@ -229,13 +227,11 @@ _io = [ ("sfp_act", 0, Pins("T25"), IOStandard("LVCMOS33")), # SFP1 - ("sfp_tx", 1, - Subsignal("p", Pins("M2")), - Subsignal("n", Pins("M1")), - ), - ("sfp_rx", 1, - Subsignal("p", Pins("N4")), - Subsignal("n", Pins("N3")), + ("sfp", 1, + Subsignal("txp", Pins("M2")), + Subsignal("txn", Pins("M1")), + Subsignal("rxp", Pins("N4")), + Subsignal("rxn", Pins("N3")), ), ("sfp_tx_disable_n", 1, Pins("N18"), IOStandard("LVCMOS33")), ("sfp_rx_los", 1, Pins("M19"), IOStandard("LVCMOS33")), @@ -243,13 +239,11 @@ _io = [ ("sfp_act", 1, Pins("R23"), IOStandard("LVCMOS33")), # SFP2 - ("sfp_tx", 2, - Subsignal("p", Pins("K2")), - Subsignal("n", Pins("K1")), - ), - ("sfp_rx", 2, - Subsignal("p", Pins("L4")), - Subsignal("n", Pins("L3")), + ("sfp", 2, + Subsignal("txp", Pins("K2")), + Subsignal("txn", Pins("K1")), + Subsignal("rxp", Pins("L4")), + Subsignal("rxn", Pins("L3")), ), ("sfp_tx_disable_n", 2, Pins("N17"), IOStandard("LVCMOS33")), ("sfp_rx_los", 2, Pins("R17"), IOStandard("LVCMOS33")), @@ -257,13 +251,11 @@ _io = [ ("sfp_act", 2, Pins("N21"), IOStandard("LVCMOS33")), # SFP3 - ("sfp_tx", 3, - Subsignal("p", Pins("H2")), - Subsignal("n", Pins("H1")), - ), - ("sfp_rx", 3, - Subsignal("p", Pins("J4")), - Subsignal("n", Pins("J3")), + ("sfp", 3, + Subsignal("txp", Pins("H2")), + Subsignal("txn", Pins("H1")), + Subsignal("rxp", Pins("J4")), + Subsignal("rxn", Pins("J3")), ), ("sfp_tx_disable_n", 3, Pins("P16"), IOStandard("LVCMOS33")), ("sfp_rx_los", 3, Pins("R16"), IOStandard("LVCMOS33")), diff --git a/litex_boards/targets/pcbarts_klusterlab.py b/litex_boards/targets/pcbarts_klusterlab.py index 496a946..c8d3d45 100755 --- a/litex_boards/targets/pcbarts_klusterlab.py +++ b/litex_boards/targets/pcbarts_klusterlab.py @@ -14,10 +14,13 @@ from litex.gen import * from litex_boards.platforms import pcbarts_klusterlab -from litex.soc.cores.clock import * +from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.builder import * -from litex.soc.cores.led import LedChaser +from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser +from litex.soc.cores.video import VideoS7HDMIPHY + +from liteeth.phy.k7_1000basex import K7_1000BASEX from litedram.modules import MT41J256M16 from litedram.common import PHYPadsReducer @@ -26,16 +29,18 @@ from litedram.phy import s7ddrphy # CRG ---------------------------------------------------------------------------------------------- class _CRG(LiteXModule): - def __init__(self, platform, sys_clk_freq): + def __init__(self, platform, sys_clk_freq, with_video_pll=False): self.rst = Signal() self.cd_sys = ClockDomain() self.cd_sys4x = ClockDomain() + self.cd_hdmi = ClockDomain() + self.cd_hdmi5x = ClockDomain() self.cd_idelay = ClockDomain() # # # - + cpu_reset = Signal() self.pll = pll = S7PLL(speedgrade=-2) - self.comb += pll.reset.eq(platform.request("cpu_reset") | self.rst) + pll.register_clkin(platform.request("clk200"), 200e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) @@ -44,18 +49,36 @@ class _CRG(LiteXModule): self.idelayctrl = S7IDELAYCTRL(self.cd_idelay) + self.comb += [ + cpu_reset.eq(platform.request("cpu_reset")), + pll.reset.eq(cpu_reset | self.rst), + ] + + # Video PLL. + if with_video_pll: + self.video_pll = video_pll = S7MMCM(speedgrade=-1) + video_pll.reset.eq(cpu_reset | self.rst) + video_pll.register_clkin(ClockSignal(), sys_clk_freq) + video_pll.create_clkout(self.cd_hdmi, 40e6) + video_pll.create_clkout(self.cd_hdmi5x, 5*40e6) + + + # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=100e6, - with_ethernet = False, - with_etherbone = False, - with_led_chaser = True, + with_ethernet = False, + with_led_chaser = True, + with_video_terminal = False, + with_video_framebuffer = False, + with_video_colorbars = False, **kwargs): platform = pcbarts_klusterlab.Platform() # CRG -------------------------------------------------------------------------------------- - self.crg = _CRG(platform, sys_clk_freq) + with_video_pll = (with_video_terminal or with_video_framebuffer or with_video_colorbars) + self.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_pll) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on PCBArts KlusterLab", **kwargs) @@ -73,6 +96,33 @@ class BaseSoC(SoCCore): l2_cache_size = kwargs.get("l2_size", 8192) ) + # Ethernet --------------------------------------------------------------------------------- + if with_ethernet: + # phy + refclk = Signal() + self.comb += [ + refclk.eq(ClockSignal("idelay")), + self.platform.request("sfp_tx_disable_n", 0).eq(1) + ] + self.ethphy = K7_1000BASEX( + refclk_or_clk_pads = refclk, + data_pads = self.platform.request("sfp", 0), + sys_clk_freq = self.clk_freq) + + self.add_ethernet(phy=self.ethphy) + self.add_etherbone(phy=self.ethphy, ip_address="192.168.0.222") + platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]") + + # Video ------------------------------------------------------------------------------------ + if (with_video_colorbars or with_video_framebuffer or with_video_terminal): + self.submodules.videophy = VideoS7HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi") + if with_video_colorbars: + self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi") + if with_video_terminal: + self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi") + if with_video_framebuffer: + self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi") + # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.leds = LedChaser( @@ -85,13 +135,22 @@ def main(): from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=pcbarts_klusterlab.Platform, description="LiteX SoC on PCBArts KlusterLab") parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.") + parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") sdopts = parser.target_group.add_mutually_exclusive_group() sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.") sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.") + viopts = parser.target_group.add_mutually_exclusive_group() + viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).") + viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).") + viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars (HDMI).") args = parser.parse_args() soc = BaseSoC( - sys_clk_freq = args.sys_clk_freq, + sys_clk_freq = args.sys_clk_freq, + with_ethernet = args.with_ethernet, + with_video_colorbars = args.with_video_colorbars, + with_video_framebuffer = args.with_video_framebuffer, + with_video_terminal = args.with_video_terminal, **parser.soc_argdict ) if args.with_spi_sdcard: