From 47659835b00f2eb10160ca8d2c3f5ab0410ee416 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 1 Mar 2023 09:37:55 +0100 Subject: [PATCH] platforms: Switch US/USP platforms to XilinxUS/USPPlatform. We were still using Xilinx7SeriesPlatform. --- litex_boards/platforms/adi_adrv2crr_fmc.py | 8 ++++---- litex_boards/platforms/alinx_axu2cga.py | 8 ++++---- litex_boards/platforms/avnet_aesku40.py | 8 ++++---- litex_boards/platforms/decklink_quad_hdmi_recorder.py | 8 ++++---- litex_boards/platforms/enclustra_mercury_xu5.py | 8 ++++---- litex_boards/platforms/opalkelly_xem8320.py | 8 ++++---- litex_boards/platforms/sqrl_fk33.py | 8 ++++---- litex_boards/platforms/sqrl_xcu1525.py | 8 ++++---- litex_boards/platforms/xilinx_alveo_u200.py | 8 ++++---- litex_boards/platforms/xilinx_alveo_u250.py | 8 ++++---- litex_boards/platforms/xilinx_alveo_u280.py | 8 ++++---- litex_boards/platforms/xilinx_kcu105.py | 8 ++++---- litex_boards/platforms/xilinx_kv260.py | 8 ++++---- litex_boards/platforms/xilinx_vcu118.py | 8 ++++---- litex_boards/platforms/xilinx_zcu102.py | 8 ++++---- litex_boards/platforms/xilinx_zcu104.py | 8 ++++---- litex_boards/platforms/xilinx_zcu106.py | 8 ++++---- litex_boards/platforms/xilinx_zcu216.py | 8 ++++---- 18 files changed, 72 insertions(+), 72 deletions(-) diff --git a/litex_boards/platforms/adi_adrv2crr_fmc.py b/litex_boards/platforms/adi_adrv2crr_fmc.py index c4c4434..cf1bacb 100644 --- a/litex_boards/platforms/adi_adrv2crr_fmc.py +++ b/litex_boards/platforms/adi_adrv2crr_fmc.py @@ -5,7 +5,7 @@ # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * -from litex.build.xilinx import Xilinx7SeriesPlatform +from litex.build.xilinx import XilinxUSPPlatform from litex.build.openocd import OpenOCD _io = [ @@ -482,15 +482,15 @@ _connectors = [ # Platform ----------------------------------------------------------------------------------------- -class Platform(Xilinx7SeriesPlatform): +class Platform(XilinxUSPPlatform): default_clk_name = "clk122m88" default_clk_period = 1e9/122.88e6 def __init__(self): - Xilinx7SeriesPlatform.__init__(self, "xczu11eg-ffvf1517-2-i", _io, _connectors, toolchain="vivado") + XilinxUSPPlatform.__init__(self, "xczu11eg-ffvf1517-2-i", _io, _connectors, toolchain="vivado") def do_finalize(self, fragment): - Xilinx7SeriesPlatform.do_finalize(self, fragment) + XilinxUSPPlatform.do_finalize(self, fragment) # Constraint self.add_period_constraint(self.lookup_request("clk122m88", loose=True), 1e9/122.88e6) diff --git a/litex_boards/platforms/alinx_axu2cga.py b/litex_boards/platforms/alinx_axu2cga.py index 766afba..1478960 100644 --- a/litex_boards/platforms/alinx_axu2cga.py +++ b/litex_boards/platforms/alinx_axu2cga.py @@ -5,7 +5,7 @@ # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * -from litex.build.xilinx import Xilinx7SeriesPlatform +from litex.build.xilinx import XilinxUSPPlatform from litex.build.openfpgaloader import OpenFPGALoader # IOs ---------------------------------------------------------------------------------------------- @@ -161,17 +161,17 @@ psu_config = { # Platform ----------------------------------------------------------------------------------------- -class Platform(Xilinx7SeriesPlatform): +class Platform(XilinxUSPPlatform): default_clk_name = "clk25" default_clk_period = 1e9/25e6 def __init__(self, toolchain="vivado"): - Xilinx7SeriesPlatform.__init__(self, "xczu2cg-sfvc784-1-e", _io, _connectors, toolchain=toolchain) + XilinxUSPPlatform.__init__(self, "xczu2cg-sfvc784-1-e", _io, _connectors, toolchain=toolchain) self.psu_config = psu_config def create_programmer(self, cable): return OpenFPGALoader("axu2cga", cable) def do_finalize(self, fragment): - Xilinx7SeriesPlatform.do_finalize(self, fragment) + XilinxUSPPlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6) diff --git a/litex_boards/platforms/avnet_aesku40.py b/litex_boards/platforms/avnet_aesku40.py index 786b6e9..408f905 100644 --- a/litex_boards/platforms/avnet_aesku40.py +++ b/litex_boards/platforms/avnet_aesku40.py @@ -5,7 +5,7 @@ # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * -from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer +from litex.build.xilinx import XilinxUSPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- @@ -182,18 +182,18 @@ _numato_sdcard_pmod_io = numato_sdcard_pmod_io("pmod0") # SDCARD PMOD on JD. # Platform ----------------------------------------------------------------------------------------- -class Platform(Xilinx7SeriesPlatform): +class Platform(XilinxUSPlatform): default_clk_name = "clk250" default_clk_period = 1e9/250e6 def __init__(self): - Xilinx7SeriesPlatform.__init__(self, "xcku040-fbva676-1-c", _io, _connectors, toolchain="vivado") + XilinxUSPlatform.__init__(self, "xcku040-fbva676-1-c", _io, _connectors, toolchain="vivado") def create_programmer(self): return VivadoProgrammer() def do_finalize(self, fragment): - Xilinx7SeriesPlatform.do_finalize(self, fragment) + XilinxUSPlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk250", loose=True), 1e9/250e6) self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 44]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 45]") diff --git a/litex_boards/platforms/decklink_quad_hdmi_recorder.py b/litex_boards/platforms/decklink_quad_hdmi_recorder.py index 07f3b20..21380a9 100644 --- a/litex_boards/platforms/decklink_quad_hdmi_recorder.py +++ b/litex_boards/platforms/decklink_quad_hdmi_recorder.py @@ -5,7 +5,7 @@ # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * -from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer +from litex.build.xilinx import XilinxUSPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- @@ -164,18 +164,18 @@ _io = [ # Platform ----------------------------------------------------------------------------------------- -class Platform(Xilinx7SeriesPlatform): +class Platform(XilinxUSPlatform): default_clk_name = "clk200" default_clk_period = 1e9/200e6 def __init__(self, toolchain="vivado"): - Xilinx7SeriesPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, toolchain=toolchain) + XilinxUSPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() def do_finalize(self, fragment): - Xilinx7SeriesPlatform.do_finalize(self, fragment) + XilinxUSPlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk24", loose=True), 1e9/24e6) self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6) self.add_platform_command("set_property INTERNAL_VREF 0.75 [get_iobanks 44]") diff --git a/litex_boards/platforms/enclustra_mercury_xu5.py b/litex_boards/platforms/enclustra_mercury_xu5.py index b55ad1a..8d5eb8b 100644 --- a/litex_boards/platforms/enclustra_mercury_xu5.py +++ b/litex_boards/platforms/enclustra_mercury_xu5.py @@ -5,7 +5,7 @@ # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * -from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer +from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- @@ -84,18 +84,18 @@ _connectors = [] # Platform ----------------------------------------------------------------------------------------- -class Platform(Xilinx7SeriesPlatform): +class Platform(XilinxUSPPlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 def __init__(self, toolchain="vivado"): - Xilinx7SeriesPlatform.__init__(self, "xczu2eg-sfvc784-1-i", _io, _connectors, toolchain=toolchain) + XilinxUSPPlatform.__init__(self, "xczu2eg-sfvc784-1-i", _io, _connectors, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() def do_finalize(self, fragment): - Xilinx7SeriesPlatform.do_finalize(self, fragment) + XilinxUSPPlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6) self.add_period_constraint(self.lookup_request("clk100_gtr", loose=True), 1e9/100e6) self.add_period_constraint(self.lookup_request("clk27_gtr", loose=True), 1e9/27e6) diff --git a/litex_boards/platforms/opalkelly_xem8320.py b/litex_boards/platforms/opalkelly_xem8320.py index ca6e158..772c738 100644 --- a/litex_boards/platforms/opalkelly_xem8320.py +++ b/litex_boards/platforms/opalkelly_xem8320.py @@ -5,7 +5,7 @@ # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * -from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer +from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- @@ -139,18 +139,18 @@ _sdcard_pmod_io = sdcard_pmod_io("pmod3") # SDCARD PMOD on JD. # Platform ----------------------------------------------------------------------------------------- -class Platform(Xilinx7SeriesPlatform): +class Platform(XilinxUSPPlatform): default_clk_name = "sys_clk100" default_clk_period = 1e9/100e6 def __init__(self, toolchain="vivado"): - Xilinx7SeriesPlatform.__init__(self, "xcau25p-ffvb676-2-e", _io, _connectors, toolchain=toolchain) + XilinxUSPPlatform.__init__(self, "xcau25p-ffvb676-2-e", _io, _connectors, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() def do_finalize(self, fragment): - Xilinx7SeriesPlatform.do_finalize(self, fragment) + XilinxUSPPlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("sys_clk100", loose=True), 1e9/100e6) self.add_period_constraint(self.lookup_request("ddr_clk100", loose=True), 1e9/100e6) self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 64]") diff --git a/litex_boards/platforms/sqrl_fk33.py b/litex_boards/platforms/sqrl_fk33.py index 0e86a52..c85a0aa 100644 --- a/litex_boards/platforms/sqrl_fk33.py +++ b/litex_boards/platforms/sqrl_fk33.py @@ -8,7 +8,7 @@ # as a generic FPGA PCIe development board: http://www.squirrelsresearch.com/forest-kitten-33 from litex.build.generic_platform import * -from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer +from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- @@ -78,18 +78,18 @@ _io = [ # Platform ----------------------------------------------------------------------------------------- -class Platform(Xilinx7SeriesPlatform): +class Platform(XilinxUSPPlatform): default_clk_name = "clk200" default_clk_period = 1e9/200e6 def __init__(self, toolchain="vivado"): - Xilinx7SeriesPlatform.__init__(self, "xcvu33p-fsvh2104-2L-e-es1", _io, toolchain=toolchain) + XilinxUSPPlatform.__init__(self, "xcvu33p-fsvh2104-2L-e-es1", _io, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() def do_finalize(self, fragment): - Xilinx7SeriesPlatform.do_finalize(self, fragment) + XilinxUSPPlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6) # Shutdown on overheatng self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]") diff --git a/litex_boards/platforms/sqrl_xcu1525.py b/litex_boards/platforms/sqrl_xcu1525.py index 416c5f7..29ede34 100644 --- a/litex_boards/platforms/sqrl_xcu1525.py +++ b/litex_boards/platforms/sqrl_xcu1525.py @@ -6,7 +6,7 @@ # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc -from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer +from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- @@ -265,18 +265,18 @@ _connectors = [] # Platform ----------------------------------------------------------------------------------------- -class Platform(Xilinx7SeriesPlatform): +class Platform(XilinxUSPPlatform): default_clk_name = "clk300" default_clk_period = 1e9/300e6 def __init__(self, toolchain="vivado"): - Xilinx7SeriesPlatform.__init__(self, "xcvu9p-fsgd2104-2l-e", _io, _connectors, toolchain=toolchain) + XilinxUSPPlatform.__init__(self, "xcvu9p-fsgd2104-2l-e", _io, _connectors, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() def do_finalize(self, fragment): - Xilinx7SeriesPlatform.do_finalize(self, fragment) + XilinxUSPPlatform.do_finalize(self, fragment) # For passively cooled boards, overheating is a significant risk if airflow isn't sufficient self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]") # Reduce programming time diff --git a/litex_boards/platforms/xilinx_alveo_u200.py b/litex_boards/platforms/xilinx_alveo_u200.py index 35f73ea..43b7dcd 100644 --- a/litex_boards/platforms/xilinx_alveo_u200.py +++ b/litex_boards/platforms/xilinx_alveo_u200.py @@ -10,7 +10,7 @@ # 1525 variants. from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc -from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer +from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer # IOs (initially auto-generated by extract_xdc_pins.py) --------------------------------------------- @@ -329,18 +329,18 @@ _connectors = [] # Platform ----------------------------------------------------------------------------------------- -class Platform(Xilinx7SeriesPlatform): +class Platform(XilinxUSPPlatform): default_clk_name = "clk300" default_clk_period = 1e9/300e6 def __init__(self, toolchain="vivado"): - Xilinx7SeriesPlatform.__init__(self, "xcu200-fsgd2104-2-e", _io, _connectors, toolchain=toolchain) + XilinxUSPPlatform.__init__(self, "xcu200-fsgd2104-2-e", _io, _connectors, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() def do_finalize(self, fragment): - Xilinx7SeriesPlatform.do_finalize(self, fragment) + XilinxUSPPlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk300", 0, loose=True), 1e9/300e6) self.add_period_constraint(self.lookup_request("clk300", 1, loose=True), 1e9/300e6) self.add_period_constraint(self.lookup_request("clk300", 2, loose=True), 1e9/300e6) diff --git a/litex_boards/platforms/xilinx_alveo_u250.py b/litex_boards/platforms/xilinx_alveo_u250.py index c549176..56547f8 100644 --- a/litex_boards/platforms/xilinx_alveo_u250.py +++ b/litex_boards/platforms/xilinx_alveo_u250.py @@ -9,7 +9,7 @@ # 1525 variants. from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc -from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer +from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer # IOs (initially auto-generated by extract_xdc_pins.py) --------------------------------------------- @@ -328,18 +328,18 @@ _connectors = [] # Platform ----------------------------------------------------------------------------------------- -class Platform(Xilinx7SeriesPlatform): +class Platform(XilinxUSPPlatform): default_clk_name = "clk300" default_clk_period = 1e9/300e6 def __init__(self, toolchain="vivado"): - Xilinx7SeriesPlatform.__init__(self, "xcu250-figd2104-2L-e", _io, _connectors, toolchain=toolchain) + XilinxUSPPlatform.__init__(self, "xcu250-figd2104-2L-e", _io, _connectors, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() def do_finalize(self, fragment): - Xilinx7SeriesPlatform.do_finalize(self, fragment) + XilinxUSPPlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk300", 0, loose=True), 1e9/300e6) self.add_period_constraint(self.lookup_request("clk300", 1, loose=True), 1e9/300e6) self.add_period_constraint(self.lookup_request("clk300", 2, loose=True), 1e9/300e6) diff --git a/litex_boards/platforms/xilinx_alveo_u280.py b/litex_boards/platforms/xilinx_alveo_u280.py index 54538aa..668dbf8 100644 --- a/litex_boards/platforms/xilinx_alveo_u280.py +++ b/litex_boards/platforms/xilinx_alveo_u280.py @@ -6,7 +6,7 @@ # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc -from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer +from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer # IOs ----------------------------------------------------------------------------------------------- @@ -220,18 +220,18 @@ _connectors = [] # Platform ----------------------------------------------------------------------------------------- -class Platform(Xilinx7SeriesPlatform): +class Platform(XilinxUSPPlatform): default_clk_name = "sysclk" default_clk_period = 1e9/100e6 def __init__(self, toolchain="vivado"): - Xilinx7SeriesPlatform.__init__(self, "xcu280-fsvh2892-2L-e-es1", _io, _connectors, toolchain=toolchain) + XilinxUSPPlatform.__init__(self, "xcu280-fsvh2892-2L-e-es1", _io, _connectors, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() def do_finalize(self, fragment): - Xilinx7SeriesPlatform.do_finalize(self, fragment) + XilinxUSPPlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("sysclk", 0, loose=True), 1e9/100e6) self.add_period_constraint(self.lookup_request("sysclk", 1, loose=True), 1e9/100e6) diff --git a/litex_boards/platforms/xilinx_kcu105.py b/litex_boards/platforms/xilinx_kcu105.py index 4df7ff9..416215e 100644 --- a/litex_boards/platforms/xilinx_kcu105.py +++ b/litex_boards/platforms/xilinx_kcu105.py @@ -5,7 +5,7 @@ # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * -from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer +from litex.build.xilinx import XilinxUSPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- @@ -518,18 +518,18 @@ _connectors = [ # Platform ----------------------------------------------------------------------------------------- -class Platform(Xilinx7SeriesPlatform): +class Platform(XilinxUSPlatform): default_clk_name = "clk125" default_clk_period = 1e9/125e6 def __init__(self, toolchain="vivado"): - Xilinx7SeriesPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors, toolchain=toolchain) + XilinxUSPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() def do_finalize(self, fragment): - Xilinx7SeriesPlatform.do_finalize(self, fragment) + XilinxUSPlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6) self.add_period_constraint(self.lookup_request("clk300", loose=True), 1e9/300e6) self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 44]") diff --git a/litex_boards/platforms/xilinx_kv260.py b/litex_boards/platforms/xilinx_kv260.py index d6c46d7..731af54 100644 --- a/litex_boards/platforms/xilinx_kv260.py +++ b/litex_boards/platforms/xilinx_kv260.py @@ -5,7 +5,7 @@ # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * -from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer +from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- @@ -21,12 +21,12 @@ _io = [ # Platform ----------------------------------------------------------------------------------------- -class Platform(Xilinx7SeriesPlatform): +class Platform(XilinxUSPPlatform): default_clk_name = "pmod_hda16_cc" default_clk_period = 1e9/100e6 def __init__(self, toolchain="vivado"): - Xilinx7SeriesPlatform.__init__(self, "xck26-sfvc784-2lv-c", _io, toolchain=toolchain) + XilinxUSPPlatform.__init__(self, "xck26-sfvc784-2lv-c", _io, toolchain=toolchain) self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", ] self.default_clk_freq = 1e9 / self.default_clk_period @@ -35,5 +35,5 @@ class Platform(Xilinx7SeriesPlatform): return VivadoProgrammer() def do_finalize(self, fragment, *args, **kwargs): - Xilinx7SeriesPlatform.do_finalize(self, fragment, *args, **kwargs) + XilinxUSPPlatform.do_finalize(self, fragment, *args, **kwargs) self.add_period_constraint(self.lookup_request("pmod_hda16_cc", loose=True), 1e9/100e6) diff --git a/litex_boards/platforms/xilinx_vcu118.py b/litex_boards/platforms/xilinx_vcu118.py index 39db77c..812f33e 100644 --- a/litex_boards/platforms/xilinx_vcu118.py +++ b/litex_boards/platforms/xilinx_vcu118.py @@ -6,7 +6,7 @@ # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * -from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer +from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- @@ -177,18 +177,18 @@ _connectors = [] # Platform ----------------------------------------------------------------------------------------- -class Platform(Xilinx7SeriesPlatform): +class Platform(XilinxUSPPlatform): default_clk_name = "clk125" default_clk_period = 1e9/125e6 def __init__(self, toolchain="vivado"): - Xilinx7SeriesPlatform.__init__(self, "xcvu9p-flga2104-2-e", _io, _connectors, toolchain="vivado") + XilinxUSPPlatform.__init__(self, "xcvu9p-flga2104-2-e", _io, _connectors, toolchain="vivado") def create_programmer(self): return VivadoProgrammer() def do_finalize(self, fragment): - Xilinx7SeriesPlatform.do_finalize(self, fragment) + XilinxUSPPlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk300", loose=True), 1e9/300e6) self.add_period_constraint(self.lookup_request("clk250", 0, loose=True), 1e9/250e6) self.add_period_constraint(self.lookup_request("clk250", 1, loose=True), 1e9/250e6) diff --git a/litex_boards/platforms/xilinx_zcu102.py b/litex_boards/platforms/xilinx_zcu102.py index 17b6aba..17b2fe3 100644 --- a/litex_boards/platforms/xilinx_zcu102.py +++ b/litex_boards/platforms/xilinx_zcu102.py @@ -5,7 +5,7 @@ # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * -from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer +from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- @@ -69,17 +69,17 @@ _io = [ # Platform ----------------------------------------------------------------------------------------- -class Platform(Xilinx7SeriesPlatform): +class Platform(XilinxUSPPlatform): default_clk_name = "clk125" default_clk_period = 1e9/125e6 def __init__(self, toolchain="vivado"): - Xilinx7SeriesPlatform.__init__(self, "xczu9eg-ffvb1156-2-i", _io, toolchain=toolchain) + XilinxUSPPlatform.__init__(self, "xczu9eg-ffvb1156-2-i", _io, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() def do_finalize(self, fragment): - Xilinx7SeriesPlatform.do_finalize(self, fragment) + XilinxUSPPlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6) self.add_period_constraint(self.lookup_request("clk300", loose=True), 1e9/300e6) diff --git a/litex_boards/platforms/xilinx_zcu104.py b/litex_boards/platforms/xilinx_zcu104.py index 364e2d0..792869f 100644 --- a/litex_boards/platforms/xilinx_zcu104.py +++ b/litex_boards/platforms/xilinx_zcu104.py @@ -6,7 +6,7 @@ # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * -from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer +from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- @@ -104,18 +104,18 @@ _io = [ # Platform ----------------------------------------------------------------------------------------- -class Platform(Xilinx7SeriesPlatform): +class Platform(XilinxUSPPlatform): default_clk_name = "clk125" default_clk_period = 1e9/125e6 def __init__(self, toolchain="vivado"): - Xilinx7SeriesPlatform.__init__(self, "xczu7ev-ffvc1156-2-i", _io, toolchain=toolchain) + XilinxUSPPlatform.__init__(self, "xczu7ev-ffvc1156-2-i", _io, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() def do_finalize(self, fragment): - Xilinx7SeriesPlatform.do_finalize(self, fragment) + XilinxUSPPlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6) self.add_period_constraint(self.lookup_request("clk300", loose=True), 1e9/125e6) self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 64]") diff --git a/litex_boards/platforms/xilinx_zcu106.py b/litex_boards/platforms/xilinx_zcu106.py index d9ddaec..b3c35cf 100644 --- a/litex_boards/platforms/xilinx_zcu106.py +++ b/litex_boards/platforms/xilinx_zcu106.py @@ -5,7 +5,7 @@ # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * -from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer +from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- @@ -120,18 +120,18 @@ _io = [ # Platform ----------------------------------------------------------------------------------------- -class Platform(Xilinx7SeriesPlatform): +class Platform(XilinxUSPPlatform): default_clk_name = "clk125" default_clk_period = 1e9/125e6 def __init__(self, toolchain="vivado"): - Xilinx7SeriesPlatform.__init__(self, "xczu7ev-ffvc1156-2-e", _io, toolchain=toolchain) + XilinxUSPPlatform.__init__(self, "xczu7ev-ffvc1156-2-e", _io, toolchain=toolchain) def create_programmer(self): return VivadoProgrammer() def do_finalize(self, fragment): - Xilinx7SeriesPlatform.do_finalize(self, fragment) + XilinxUSPPlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6) self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 64]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 65]") diff --git a/litex_boards/platforms/xilinx_zcu216.py b/litex_boards/platforms/xilinx_zcu216.py index 48b33b1..d2e39c2 100644 --- a/litex_boards/platforms/xilinx_zcu216.py +++ b/litex_boards/platforms/xilinx_zcu216.py @@ -5,7 +5,7 @@ # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * -from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer +from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- @@ -28,12 +28,12 @@ _io = [ # Platform ----------------------------------------------------------------------------------------- -class Platform(Xilinx7SeriesPlatform): +class Platform(XilinxUSPPlatform): default_clk_name = "clk100" default_clk_period = 1e9 / 100e6 def __init__(self, toolchain="vivado"): - Xilinx7SeriesPlatform.__init__(self, "xczu49dr-ffvf1760-2-e", _io, toolchain=toolchain) + XilinxUSPPlatform.__init__(self, "xczu49dr-ffvf1760-2-e", _io, toolchain=toolchain) self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", ] self.default_clk_freq = 1e9 / self.default_clk_period @@ -42,5 +42,5 @@ class Platform(Xilinx7SeriesPlatform): return VivadoProgrammer() def do_finalize(self, fragment, *args, **kwargs): - Xilinx7SeriesPlatform.do_finalize(self, fragment, *args, **kwargs) + XilinxUSPPlatform.do_finalize(self, fragment, *args, **kwargs) self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True), self.default_clk_period)