From 47bdf5f759e43ae9fbce5d5725c7cf00a8d00a44 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 25 Mar 2021 10:11:24 +0100 Subject: [PATCH] targets: Use new CSR automatic allocation (self.add_csr will still work but is no longer required). --- litex_boards/targets/ac701.py | 4 ---- litex_boards/targets/acorn_cle_215.py | 4 ---- litex_boards/targets/aller.py | 3 --- litex_boards/targets/alveo_u250.py | 3 --- litex_boards/targets/alveo_u280.py | 4 ---- litex_boards/targets/arrow_sockit.py | 1 - litex_boards/targets/arty.py | 3 --- litex_boards/targets/arty_s7.py | 2 -- litex_boards/targets/c10lprefkit.py | 2 -- litex_boards/targets/camlink_4k.py | 2 -- litex_boards/targets/colorlight_5a_75x.py | 2 -- litex_boards/targets/colorlight_i5.py | 3 --- litex_boards/targets/crosslink_nx_evn.py | 2 -- litex_boards/targets/crosslink_nx_vip.py | 2 -- litex_boards/targets/de0nano.py | 1 - litex_boards/targets/de10lite.py | 1 - litex_boards/targets/de10nano.py | 1 - litex_boards/targets/deca.py | 1 - litex_boards/targets/ecp5_evn.py | 1 - litex_boards/targets/ecpix5.py | 3 --- litex_boards/targets/fk33.py | 4 ---- litex_boards/targets/fomu.py | 1 - litex_boards/targets/fpc_iii.py | 3 --- litex_boards/targets/genesys2.py | 3 --- litex_boards/targets/icebreaker.py | 1 - litex_boards/targets/kc705.py | 5 ----- litex_boards/targets/kcu105.py | 5 ----- litex_boards/targets/kx2.py | 2 -- litex_boards/targets/linsn_rv901t.py | 2 -- litex_boards/targets/litefury.py | 3 --- litex_boards/targets/logicbone.py | 3 --- litex_boards/targets/mercury_xu5.py | 2 -- litex_boards/targets/mimas_a7.py | 3 --- litex_boards/targets/minispartan6.py | 1 - litex_boards/targets/mist.py | 1 - litex_boards/targets/nereid.py | 2 -- litex_boards/targets/netv2.py | 4 ---- litex_boards/targets/nexys4ddr.py | 3 --- litex_boards/targets/nexys_video.py | 4 ---- litex_boards/targets/orangecrab.py | 2 -- litex_boards/targets/pano_logic_g2.py | 4 +--- litex_boards/targets/pipistrello.py | 2 -- litex_boards/targets/qmtech_ep4ce15.py | 1 - litex_boards/targets/qmtech_wukong.py | 3 --- litex_boards/targets/redpitaya.py | 1 - litex_boards/targets/sds1104xe.py | 2 -- litex_boards/targets/simple.py | 1 - litex_boards/targets/tagus.py | 3 --- litex_boards/targets/tec0117.py | 1 - litex_boards/targets/tinyfpga_bx.py | 1 - litex_boards/targets/trellisboard.py | 3 --- litex_boards/targets/ulx3s.py | 3 --- litex_boards/targets/vc707.py | 3 --- litex_boards/targets/vcu118.py | 2 -- litex_boards/targets/versa_ecp5.py | 3 --- litex_boards/targets/xcu1525.py | 4 ---- litex_boards/targets/zcu104.py | 2 -- litex_boards/targets/ztex213.py | 2 -- litex_boards/targets/zybo_z7.py | 1 - 59 files changed, 1 insertion(+), 140 deletions(-) diff --git a/litex_boards/targets/ac701.py b/litex_boards/targets/ac701.py index d864ebc..21b4b23 100755 --- a/litex_boards/targets/ac701.py +++ b/litex_boards/targets/ac701.py @@ -75,7 +75,6 @@ class BaseSoC(SoCCore): memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT8JTF12864(sys_clk_freq, "1:4"), @@ -94,7 +93,6 @@ class BaseSoC(SoCCore): self.submodules.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) - self.add_csr("ethphy") # 1000BaseX Ethernet PHY --------------------------------------------------------------- if eth_phy == "1000basex": @@ -129,14 +127,12 @@ class BaseSoC(SoCCore): self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) - self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- def main(): diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py index 5144b45..48e77ab 100755 --- a/litex_boards/targets/acorn_cle_215.py +++ b/litex_boards/targets/acorn_cle_215.py @@ -91,7 +91,6 @@ class BaseSoC(SoCCore): nphases = 4, sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41K512M16(sys_clk_freq, "1:4"), @@ -107,7 +106,6 @@ class BaseSoC(SoCCore): self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) - self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1) # SATA ------------------------------------------------------------------------------------- @@ -140,7 +138,6 @@ class BaseSoC(SoCCore): gen = "gen2", clk_freq = sys_clk_freq, data_width = 16) - self.add_csr("sata_phy") # Core self.add_sata(phy=self.sata_phy, mode="read+write") @@ -149,7 +146,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py index fbb8642..dcbd7db 100755 --- a/litex_boards/targets/aller.py +++ b/litex_boards/targets/aller.py @@ -75,7 +75,6 @@ class BaseSoC(SoCCore): nphases = 4, sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41J128M16(sys_clk_freq, "1:4"), @@ -91,14 +90,12 @@ class BaseSoC(SoCCore): self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) - self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/alveo_u250.py b/litex_boards/targets/alveo_u250.py index 8dd4d2c..1c0e177 100755 --- a/litex_boards/targets/alveo_u250.py +++ b/litex_boards/targets/alveo_u250.py @@ -77,7 +77,6 @@ class BaseSoC(SoCCore): sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 500e6, is_rdimm = True) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"), @@ -96,14 +95,12 @@ class BaseSoC(SoCCore): self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) - self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/alveo_u280.py b/litex_boards/targets/alveo_u280.py index d901762..24ef2d3 100755 --- a/litex_boards/targets/alveo_u280.py +++ b/litex_boards/targets/alveo_u280.py @@ -64,7 +64,6 @@ class BaseSoC(SoCCore): SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Alveo U280", ident_version = True, - # bus_standard = "axi-lite", # **kwargs) # CRG -------------------------------------------------------------------------------------- @@ -77,7 +76,6 @@ class BaseSoC(SoCCore): sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 500e6, is_rdimm = True) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"), @@ -96,14 +94,12 @@ class BaseSoC(SoCCore): self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) - self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("gpio_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/arrow_sockit.py b/litex_boards/targets/arrow_sockit.py index 030a083..2ec8af2 100755 --- a/litex_boards/targets/arrow_sockit.py +++ b/litex_boards/targets/arrow_sockit.py @@ -130,7 +130,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") if mister_sdram == "xs_v22": sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY diff --git a/litex_boards/targets/arty.py b/litex_boards/targets/arty.py index 5a9064b..5160653 100755 --- a/litex_boards/targets/arty.py +++ b/litex_boards/targets/arty.py @@ -73,7 +73,6 @@ class BaseSoC(SoCCore): memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41K128M16(sys_clk_freq, "1:4"), @@ -89,7 +88,6 @@ class BaseSoC(SoCCore): self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) - self.add_csr("ethphy") if with_ethernet: self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) if with_etherbone: @@ -103,7 +101,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/arty_s7.py b/litex_boards/targets/arty_s7.py index 97e1373..87f0733 100755 --- a/litex_boards/targets/arty_s7.py +++ b/litex_boards/targets/arty_s7.py @@ -69,7 +69,6 @@ class BaseSoC(SoCCore): memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41K128M16(sys_clk_freq, "1:4"), @@ -84,7 +83,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/c10lprefkit.py b/litex_boards/targets/c10lprefkit.py index 98a59e9..7a6e045 100755 --- a/litex_boards/targets/c10lprefkit.py +++ b/litex_boards/targets/c10lprefkit.py @@ -93,14 +93,12 @@ class BaseSoC(SoCCore): self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) - self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/camlink_4k.py b/litex_boards/targets/camlink_4k.py index ab32980..93a61bd 100755 --- a/litex_boards/targets/camlink_4k.py +++ b/litex_boards/targets/camlink_4k.py @@ -90,7 +90,6 @@ class BaseSoC(SoCCore): self.submodules.ddrphy = ECP5DDRPHY( platform.request("ddram"), sys_clk_freq=sys_clk_freq) - self.add_csr("ddrphy") self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.add_sdram("sdram", phy = self.ddrphy, @@ -107,7 +106,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/colorlight_5a_75x.py b/litex_boards/targets/colorlight_5a_75x.py index 5f56f85..a5d4d80 100755 --- a/litex_boards/targets/colorlight_5a_75x.py +++ b/litex_boards/targets/colorlight_5a_75x.py @@ -167,7 +167,6 @@ class BaseSoC(SoCCore): clock_pads = self.platform.request("eth_clocks", eth_phy), pads = self.platform.request("eth", eth_phy), tx_delay = 0e-9) - self.add_csr("ethphy") if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: @@ -178,7 +177,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led_n"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/colorlight_i5.py b/litex_boards/targets/colorlight_i5.py index 00313be..7c73fb7 100755 --- a/litex_boards/targets/colorlight_i5.py +++ b/litex_boards/targets/colorlight_i5.py @@ -122,7 +122,6 @@ class BaseSoC(SoCCore): # Leds ------------------------------------------------------------------------------------- ledn = platform.request_all("user_led_n") self.submodules.leds = LedChaser(pads=ledn, sys_clk_freq=sys_clk_freq) - self.add_csr("leds") # SPI Flash -------------------------------------------------------------------------------- self.add_spi_flash(mode="1x", dummy_cycles=8) @@ -151,7 +150,6 @@ class BaseSoC(SoCCore): clock_pads = self.platform.request("eth_clocks", eth_phy), pads = self.platform.request("eth", eth_phy), tx_delay = 0) - self.add_csr("ethphy") if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: @@ -174,7 +172,6 @@ class BaseSoC(SoCCore): # PRBS ------------------------------------------------------------------------------------- if with_prbs: self.submodules.prbs = _PRBSSource() - self.add_csr("prbs") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/crosslink_nx_evn.py b/litex_boards/targets/crosslink_nx_evn.py index 4409908..69406ef 100755 --- a/litex_boards/targets/crosslink_nx_evn.py +++ b/litex_boards/targets/crosslink_nx_evn.py @@ -96,8 +96,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = Cat(*[platform.request("user_led", i) for i in range(14)]), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") - # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/crosslink_nx_vip.py b/litex_boards/targets/crosslink_nx_vip.py index f79cace..a44e6d7 100755 --- a/litex_boards/targets/crosslink_nx_vip.py +++ b/litex_boards/targets/crosslink_nx_vip.py @@ -101,8 +101,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = Cat(*[platform.request("user_led", i) for i in range(4)]), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") - # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/de0nano.py b/litex_boards/targets/de0nano.py index 730c9fe..54887fb 100755 --- a/litex_boards/targets/de0nano.py +++ b/litex_boards/targets/de0nano.py @@ -89,7 +89,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/de10lite.py b/litex_boards/targets/de10lite.py index c0276d6..2bb6e38 100755 --- a/litex_boards/targets/de10lite.py +++ b/litex_boards/targets/de10lite.py @@ -88,7 +88,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/de10nano.py b/litex_boards/targets/de10nano.py index 35d96f5..1f1f3b7 100755 --- a/litex_boards/targets/de10nano.py +++ b/litex_boards/targets/de10nano.py @@ -99,7 +99,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/deca.py b/litex_boards/targets/deca.py index 176efe2..ae74121 100755 --- a/litex_boards/targets/deca.py +++ b/litex_boards/targets/deca.py @@ -71,7 +71,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/ecp5_evn.py b/litex_boards/targets/ecp5_evn.py index 1d473ef..3ce9335 100755 --- a/litex_boards/targets/ecp5_evn.py +++ b/litex_boards/targets/ecp5_evn.py @@ -62,7 +62,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/ecpix5.py b/litex_boards/targets/ecpix5.py index 4513520..31d2d31 100755 --- a/litex_boards/targets/ecpix5.py +++ b/litex_boards/targets/ecpix5.py @@ -95,7 +95,6 @@ class BaseSoC(SoCCore): self.submodules.ddrphy = ECP5DDRPHY( platform.request("ddram"), sys_clk_freq=sys_clk_freq) - self.add_csr("ddrphy") self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", @@ -114,7 +113,6 @@ class BaseSoC(SoCCore): clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth"), rx_delay = 0e-9) - self.add_csr("ethphy") if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: @@ -129,7 +127,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = Cat(leds_pads), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/fk33.py b/litex_boards/targets/fk33.py index 80b84a9..f5f7454 100755 --- a/litex_boards/targets/fk33.py +++ b/litex_boards/targets/fk33.py @@ -63,7 +63,6 @@ class BaseSoC(SoCCore): data_width = 128, bar0_size = 0x20000) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) - self.add_csr("pcie_phy") # Endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8) @@ -77,13 +76,11 @@ class BaseSoC(SoCCore): self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering = True, buffering_depth=1024, with_loopback = True) - self.add_csr("pcie_dma0") self.add_constant("DMA_CHANNELS", 1) # MSI self.submodules.pcie_msi = LitePCIeMSI() - self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, @@ -97,7 +94,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/fomu.py b/litex_boards/targets/fomu.py index b6952bb..da5e815 100755 --- a/litex_boards/targets/fomu.py +++ b/litex_boards/targets/fomu.py @@ -113,7 +113,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led_n"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Flash -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/fpc_iii.py b/litex_boards/targets/fpc_iii.py index 014ba5a..15721d5 100755 --- a/litex_boards/targets/fpc_iii.py +++ b/litex_boards/targets/fpc_iii.py @@ -105,7 +105,6 @@ class BaseSoC(SoCCore): self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.comb += ddram.vccio.eq(Replicate(C(1), ddram.vccio.nbits)) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = IS43TR16256A(sys_clk_freq, "1:2"), @@ -122,7 +121,6 @@ class BaseSoC(SoCCore): self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) - self.add_csr("ethphy") if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: @@ -132,7 +130,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/genesys2.py b/litex_boards/targets/genesys2.py index 44f29ec..53ff10b 100755 --- a/litex_boards/targets/genesys2.py +++ b/litex_boards/targets/genesys2.py @@ -65,7 +65,6 @@ class BaseSoC(SoCCore): memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41J256M16(sys_clk_freq, "1:4"), @@ -81,7 +80,6 @@ class BaseSoC(SoCCore): self.submodules.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) - self.add_csr("ethphy") if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: @@ -91,7 +89,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/icebreaker.py b/litex_boards/targets/icebreaker.py index 0028211..29235d3 100755 --- a/litex_boards/targets/icebreaker.py +++ b/litex_boards/targets/icebreaker.py @@ -114,7 +114,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Flash -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/kc705.py b/litex_boards/targets/kc705.py index d2d17b9..7e494d8 100755 --- a/litex_boards/targets/kc705.py +++ b/litex_boards/targets/kc705.py @@ -70,7 +70,6 @@ class BaseSoC(SoCCore): memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT8JTF12864(sys_clk_freq, "1:4"), @@ -87,7 +86,6 @@ class BaseSoC(SoCCore): clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth"), clk_freq = self.clk_freq) - self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # PCIe ------------------------------------------------------------------------------------- @@ -95,7 +93,6 @@ class BaseSoC(SoCCore): self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) - self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1) # SATA ------------------------------------------------------------------------------------- @@ -128,7 +125,6 @@ class BaseSoC(SoCCore): gen = "gen2", clk_freq = sys_clk_freq, data_width = 16) - self.add_csr("sata_phy") # Core self.add_sata(phy=self.sata_phy, mode="read+write") @@ -137,7 +133,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py index d171314..b0af4fc 100755 --- a/litex_boards/targets/kcu105.py +++ b/litex_boards/targets/kcu105.py @@ -79,7 +79,6 @@ class BaseSoC(SoCCore): memtype = "DDR4", sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = EDY4016A(sys_clk_freq, "1:4"), @@ -95,7 +94,6 @@ class BaseSoC(SoCCore): self.submodules.ethphy = KU_1000BASEX(self.crg.cd_eth.clk, data_pads = self.platform.request("sfp", 0), sys_clk_freq = self.clk_freq) - self.add_csr("ethphy") self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1) self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]") if with_ethernet: @@ -108,7 +106,6 @@ class BaseSoC(SoCCore): self.submodules.pcie_phy = USPCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) - self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1) # SATA ------------------------------------------------------------------------------------- @@ -141,7 +138,6 @@ class BaseSoC(SoCCore): gen = "gen2", clk_freq = sys_clk_freq, data_width = 16) - self.add_csr("sata_phy") # Core self.add_sata(phy=self.sata_phy, mode="read+write") @@ -150,7 +146,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/kx2.py b/litex_boards/targets/kx2.py index 958a8af..9e845e2 100755 --- a/litex_boards/targets/kx2.py +++ b/litex_boards/targets/kx2.py @@ -64,7 +64,6 @@ class BaseSoC(SoCCore): memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = H5TC4G63CFR(sys_clk_freq, "1:4"), @@ -79,7 +78,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = Cat(*[platform.request("user_led", i) for i in range(4)]), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/linsn_rv901t.py b/litex_boards/targets/linsn_rv901t.py index 34e980d..4726555 100755 --- a/litex_boards/targets/linsn_rv901t.py +++ b/litex_boards/targets/linsn_rv901t.py @@ -80,14 +80,12 @@ class BaseSoC(SoCCore): self.submodules.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks", eth_phy), pads = self.platform.request("eth", eth_phy)) - self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/litefury.py b/litex_boards/targets/litefury.py index d0ce977..4131439 100755 --- a/litex_boards/targets/litefury.py +++ b/litex_boards/targets/litefury.py @@ -75,7 +75,6 @@ class BaseSoC(SoCCore): nphases = 4, sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = AS4C256M16D3A(sys_clk_freq, "1:4"), @@ -91,14 +90,12 @@ class BaseSoC(SoCCore): self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 64, bar0_size = 0x20000) - self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/logicbone.py b/litex_boards/targets/logicbone.py index 18084fa..9053dd6 100755 --- a/litex_boards/targets/logicbone.py +++ b/litex_boards/targets/logicbone.py @@ -125,7 +125,6 @@ class BaseSoC(SoCCore): self.submodules.ddrphy = ECP5DDRPHY( platform.request("ddram"), sys_clk_freq=sys_clk_freq) - self.add_csr("ddrphy") self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", @@ -143,7 +142,6 @@ class BaseSoC(SoCCore): self.submodules.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) - self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) @@ -151,7 +149,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/mercury_xu5.py b/litex_boards/targets/mercury_xu5.py index 9e35d92..5d27f9a 100755 --- a/litex_boards/targets/mercury_xu5.py +++ b/litex_boards/targets/mercury_xu5.py @@ -72,7 +72,6 @@ class BaseSoC(SoCCore): memtype = "DDR4", sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 500e6) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT40A256M16(sys_clk_freq, "1:4"), @@ -87,7 +86,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/mimas_a7.py b/litex_boards/targets/mimas_a7.py index 8268ece..01fcf19 100755 --- a/litex_boards/targets/mimas_a7.py +++ b/litex_boards/targets/mimas_a7.py @@ -69,7 +69,6 @@ class BaseSoC(SoCCore): memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41J128M16(sys_clk_freq, "1:4"), @@ -85,14 +84,12 @@ class BaseSoC(SoCCore): self.submodules.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) - self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/minispartan6.py b/litex_boards/targets/minispartan6.py index bf416dd..d30bd05 100755 --- a/litex_boards/targets/minispartan6.py +++ b/litex_boards/targets/minispartan6.py @@ -106,7 +106,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/mist.py b/litex_boards/targets/mist.py index 68aeaa4..609a5f1 100755 --- a/litex_boards/targets/mist.py +++ b/litex_boards/targets/mist.py @@ -88,7 +88,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py index 71dab2a..01e9ed6 100755 --- a/litex_boards/targets/nereid.py +++ b/litex_boards/targets/nereid.py @@ -72,7 +72,6 @@ class BaseSoC(SoCCore): nphases = 4, sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT8KTF51264(sys_clk_freq, "1:4", speedgrade="800"), @@ -88,7 +87,6 @@ class BaseSoC(SoCCore): self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) - self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/netv2.py b/litex_boards/targets/netv2.py index fa3921a..7deec15 100755 --- a/litex_boards/targets/netv2.py +++ b/litex_boards/targets/netv2.py @@ -79,7 +79,6 @@ class BaseSoC(SoCCore): memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = K4B2G1646F(sys_clk_freq, "1:4"), @@ -95,7 +94,6 @@ class BaseSoC(SoCCore): self.submodules.ethphy = LiteEthPHYRMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) - self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # PCIe ------------------------------------------------------------------------------------- @@ -103,14 +101,12 @@ class BaseSoC(SoCCore): self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) - self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1, max_pending_requests=2) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/nexys4ddr.py b/litex_boards/targets/nexys4ddr.py index 0eef966..8152978 100755 --- a/litex_boards/targets/nexys4ddr.py +++ b/litex_boards/targets/nexys4ddr.py @@ -72,7 +72,6 @@ class BaseSoC(SoCCore): memtype = "DDR2", nphases = 2, sys_clk_freq = sys_clk_freq) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT47H64M16(sys_clk_freq, "1:2"), @@ -88,7 +87,6 @@ class BaseSoC(SoCCore): self.submodules.ethphy = LiteEthPHYRMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) - self.add_csr("ethphy") if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: @@ -106,7 +104,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/nexys_video.py b/litex_boards/targets/nexys_video.py index 53ebf8d..5a6bc51 100755 --- a/litex_boards/targets/nexys_video.py +++ b/litex_boards/targets/nexys_video.py @@ -78,7 +78,6 @@ class BaseSoC(SoCCore): memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41K256M16(sys_clk_freq, "1:4"), @@ -94,7 +93,6 @@ class BaseSoC(SoCCore): self.submodules.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) - self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # SATA ------------------------------------------------------------------------------------- @@ -122,7 +120,6 @@ class BaseSoC(SoCCore): gen = "gen2", clk_freq = sys_clk_freq, data_width = 16) - self.add_csr("sata_phy") # Core self.add_sata(phy=self.sata_phy, mode="read+write") @@ -139,7 +136,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index 562d854..9fea8f0 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -184,7 +184,6 @@ class BaseSoC(SoCCore): sys_clk_freq = sys_clk_freq, cmd_delay = 0 if sys_clk_freq > 64e6 else 100) self.ddrphy.settings.rtt_nom = "disabled" - self.add_csr("ddrphy") if hasattr(ddram_pads, "vccio"): self.comb += ddram_pads.vccio.eq(0b111111) if hasattr(ddram_pads, "gnd"): @@ -205,7 +204,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/pano_logic_g2.py b/litex_boards/targets/pano_logic_g2.py index 93b9094..a42051e 100755 --- a/litex_boards/targets/pano_logic_g2.py +++ b/litex_boards/targets/pano_logic_g2.py @@ -65,7 +65,6 @@ class BaseSoC(SoCCore): pads = self.platform.request("eth"), clk_freq = sys_clk_freq, with_hw_init_reset = False) - self.add_csr("ethphy") if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: @@ -75,7 +74,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- @@ -85,7 +83,7 @@ def main(): parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--revision", default="c", help="Board revision c (default) or b") parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") - ethopts = parser.add_mutually_exclusive_group() + ethopts = parser.add_mutually_exclusive_group() ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address") diff --git a/litex_boards/targets/pipistrello.py b/litex_boards/targets/pipistrello.py index 9c2031b..74cd6e6 100755 --- a/litex_boards/targets/pipistrello.py +++ b/litex_boards/targets/pipistrello.py @@ -178,7 +178,6 @@ class BaseSoC(SoCCore): self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), ] - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT46H32M16(sys_clk_freq, "1:2"), @@ -193,7 +192,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/qmtech_ep4ce15.py b/litex_boards/targets/qmtech_ep4ce15.py index f8a4376..5ea64e4 100755 --- a/litex_boards/targets/qmtech_ep4ce15.py +++ b/litex_boards/targets/qmtech_ep4ce15.py @@ -89,7 +89,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/qmtech_wukong.py b/litex_boards/targets/qmtech_wukong.py index 407e905..7eb4945 100755 --- a/litex_boards/targets/qmtech_wukong.py +++ b/litex_boards/targets/qmtech_wukong.py @@ -71,7 +71,6 @@ class BaseSoC(SoCCore): memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41K128M16(sys_clk_freq, "1:4"), @@ -87,7 +86,6 @@ class BaseSoC(SoCCore): self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) - self.add_csr("ethphy") if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: @@ -97,7 +95,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/redpitaya.py b/litex_boards/targets/redpitaya.py index b594447..4f959ca 100755 --- a/litex_boards/targets/redpitaya.py +++ b/litex_boards/targets/redpitaya.py @@ -86,7 +86,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/sds1104xe.py b/litex_boards/targets/sds1104xe.py index eb9ac38..f44a051 100755 --- a/litex_boards/targets/sds1104xe.py +++ b/litex_boards/targets/sds1104xe.py @@ -80,7 +80,6 @@ class BaseSoC(SoCCore): memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41K64M16(sys_clk_freq, "1:4"), @@ -120,7 +119,6 @@ class BaseSoC(SoCCore): # Software Interface. self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) - self.add_csr("ethmac") if self.irq.enabled: self.irq.add("ethmac", use_loc_if_exists=True) diff --git a/litex_boards/targets/simple.py b/litex_boards/targets/simple.py index 7efef10..73762fa 100755 --- a/litex_boards/targets/simple.py +++ b/litex_boards/targets/simple.py @@ -40,7 +40,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") except: pass diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py index b1d7191..153c80e 100755 --- a/litex_boards/targets/tagus.py +++ b/litex_boards/targets/tagus.py @@ -76,7 +76,6 @@ class BaseSoC(SoCCore): nphases = 4, sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41J128M16(sys_clk_freq, "1:4"), @@ -92,14 +91,12 @@ class BaseSoC(SoCCore): self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), data_width = 128, bar0_size = 0x20000) - self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/tec0117.py b/litex_boards/targets/tec0117.py index 7fbda89..40e1173 100755 --- a/litex_boards/targets/tec0117.py +++ b/litex_boards/targets/tec0117.py @@ -120,7 +120,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Flash -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/tinyfpga_bx.py b/litex_boards/targets/tinyfpga_bx.py index 52fb789..ad847fe 100755 --- a/litex_boards/targets/tinyfpga_bx.py +++ b/litex_boards/targets/tinyfpga_bx.py @@ -61,7 +61,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index 83f5ace..88c7c6b 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -131,7 +131,6 @@ class BaseSoC(SoCCore): sys_clk_freq=sys_clk_freq) self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41J256M16(sys_clk_freq, "1:2"), @@ -147,14 +146,12 @@ class BaseSoC(SoCCore): self.submodules.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) - self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py index eeceb41..09b7654 100755 --- a/litex_boards/targets/ulx3s.py +++ b/litex_boards/targets/ulx3s.py @@ -134,17 +134,14 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") def add_oled(self): pads = self.platform.request("oled_spi") pads.miso = Signal() self.submodules.oled_spi = SPIMaster(pads, 8, self.sys_clk_freq, 8e6) self.oled_spi.add_clk_divider() - self.add_csr("oled_spi") self.submodules.oled_ctl = GPIOOut(self.platform.request("oled_ctl")) - self.add_csr("oled_ctl") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/vc707.py b/litex_boards/targets/vc707.py index 352e89e..d8e1680 100755 --- a/litex_boards/targets/vc707.py +++ b/litex_boards/targets/vc707.py @@ -66,7 +66,6 @@ class BaseSoC(SoCCore): memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT8JTF12864(sys_clk_freq, "1:4"), @@ -82,14 +81,12 @@ class BaseSoC(SoCCore): self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) - self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/vcu118.py b/litex_boards/targets/vcu118.py index 73adf2c..f85d0a7 100755 --- a/litex_boards/targets/vcu118.py +++ b/litex_boards/targets/vcu118.py @@ -73,7 +73,6 @@ class BaseSoC(SoCCore): memtype = "DDR4", sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 500e6) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = EDY4016A(sys_clk_freq, "1:4"), @@ -88,7 +87,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index 694d436..19d41d1 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -99,7 +99,6 @@ class BaseSoC(SoCCore): self.submodules.ddrphy = ECP5DDRPHY( platform.request("ddram"), sys_clk_freq=sys_clk_freq) - self.add_csr("ddrphy") self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", @@ -119,7 +118,6 @@ class BaseSoC(SoCCore): pads = self.platform.request("eth", eth_phy), tx_delay = 0e-9, rx_delay = 0e-9) - self.add_csr("ethphy") if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: @@ -129,7 +127,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/xcu1525.py b/litex_boards/targets/xcu1525.py index 6b0215d..c26a87e 100755 --- a/litex_boards/targets/xcu1525.py +++ b/litex_boards/targets/xcu1525.py @@ -76,7 +76,6 @@ class BaseSoC(SoCCore): memtype = "DDR4", sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 500e6) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT40A512M8(sys_clk_freq, "1:4"), @@ -94,7 +93,6 @@ class BaseSoC(SoCCore): self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) - self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1) # SATA ------------------------------------------------------------------------------------- @@ -126,7 +124,6 @@ class BaseSoC(SoCCore): gen = "gen2", clk_freq = sys_clk_freq, data_width = 16) - self.add_csr("sata_phy") # Core self.add_sata(phy=self.sata_phy, mode="read+write") @@ -135,7 +132,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/zcu104.py b/litex_boards/targets/zcu104.py index c152f60..8b98948 100755 --- a/litex_boards/targets/zcu104.py +++ b/litex_boards/targets/zcu104.py @@ -74,7 +74,6 @@ class BaseSoC(SoCCore): memtype = "DDR4", sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 500e6) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MTA4ATF51264HZ(sys_clk_freq, "1:4"), @@ -89,7 +88,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/ztex213.py b/litex_boards/targets/ztex213.py index b3a7b3e..dbf4dcb 100755 --- a/litex_boards/targets/ztex213.py +++ b/litex_boards/targets/ztex213.py @@ -82,7 +82,6 @@ class BaseSoC(SoCCore): memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41J128M16(sys_clk_freq, "1:4"), #MT41J128M16XX-125 @@ -97,7 +96,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/zybo_z7.py b/litex_boards/targets/zybo_z7.py index a377c0c..10c56de 100755 --- a/litex_boards/targets/zybo_z7.py +++ b/litex_boards/targets/zybo_z7.py @@ -79,7 +79,6 @@ class BaseSoC(SoCCore): self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Build --------------------------------------------------------------------------------------------