diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py
index ad709b4..b428600 100755
--- a/litex_boards/targets/acorn_cle_215.py
+++ b/litex_boards/targets/acorn_cle_215.py
@@ -137,7 +137,7 @@ class PCIeSoC(SoCCore):
         # PCIe -------------------------------------------------------------------------------------
         # PHY
         self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
-            data_width = 64,
+            data_width = 128,
             bar0_size  = 0x20000)
         self.pcie_phy.add_timing_constraints(platform)
         platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
@@ -145,7 +145,7 @@ class PCIeSoC(SoCCore):
         self.comb += platform.request("pcie_clkreq_n").eq(0)
 
         # Endpoint
-        self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
+        self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8)
 
         # Wishbone bridge
         self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py
index 8a396a1..2a3d25d 100755
--- a/litex_boards/targets/aller.py
+++ b/litex_boards/targets/aller.py
@@ -116,14 +116,14 @@ class PCIeSoC(SoCCore):
         # PCIe -------------------------------------------------------------------------------------
         # PHY
         self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
-            data_width = 64,
+            data_width = 128,
             bar0_size  = 0x20000)
         self.pcie_phy.add_timing_constraints(platform)
         platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
         self.add_csr("pcie_phy")
 
         # Endpoint
-        self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
+        self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8)
 
         # Wishbone bridge
         self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py
index 8ffe98c..3a48521 100755
--- a/litex_boards/targets/nereid.py
+++ b/litex_boards/targets/nereid.py
@@ -115,14 +115,14 @@ class PCIeSoC(SoCCore):
         # PCIe -------------------------------------------------------------------------------------
         # PHY
         self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
-            data_width = 64,
+            data_width = 128,
             bar0_size  = 0x20000)
         self.pcie_phy.add_timing_constraints(platform)
         platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
         self.add_csr("pcie_phy")
 
         # Endpoint
-        self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
+        self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8)
 
         # Wishbone bridge
         self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,