From 48476be9e2fd6d4bb5751c1aa786a30b62197eed Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 14 Dec 2019 22:10:04 +0100 Subject: [PATCH] aller/nereid/tagus: LitePCIeWishboneBridge's shadow_base replace with base_address --- litex_boards/partner/targets/aller.py | 2 +- litex_boards/partner/targets/nereid.py | 2 +- litex_boards/partner/targets/tagus.py | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/litex_boards/partner/targets/aller.py b/litex_boards/partner/targets/aller.py index 5ddb25d..1504a4e 100755 --- a/litex_boards/partner/targets/aller.py +++ b/litex_boards/partner/targets/aller.py @@ -103,7 +103,7 @@ class AllerSoC(SoCSDRAM): # pcie wishbone bridge self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, - lambda a: 1, shadow_base=self.mem_map["csr"]) + lambda a: 1, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma diff --git a/litex_boards/partner/targets/nereid.py b/litex_boards/partner/targets/nereid.py index b7bde0d..11b5588 100755 --- a/litex_boards/partner/targets/nereid.py +++ b/litex_boards/partner/targets/nereid.py @@ -103,7 +103,7 @@ class NereidSoC(SoCSDRAM): # pcie wishbone bridge self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, - lambda a: 1, shadow_base=self.mem_map["csr"]) + lambda a: 1, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma diff --git a/litex_boards/partner/targets/tagus.py b/litex_boards/partner/targets/tagus.py index 42d7b39..38eb92a 100755 --- a/litex_boards/partner/targets/tagus.py +++ b/litex_boards/partner/targets/tagus.py @@ -105,7 +105,7 @@ class TagusSoC(SoCSDRAM): # pcie wishbone bridge self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, - lambda a: 1, shadow_base=self.mem_map["csr"]) + lambda a: 1, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma