From 496cae54ff620f42e3c7f47683e5573fd54d397d Mon Sep 17 00:00:00 2001 From: gatecat Date: Mon, 8 Mar 2021 14:26:40 +0000 Subject: [PATCH] crosslink_nx_vip: Remove constraint for MIPI pins Signed-off-by: gatecat --- litex_boards/platforms/crosslink_nx_vip.py | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/litex_boards/platforms/crosslink_nx_vip.py b/litex_boards/platforms/crosslink_nx_vip.py index d125310..811d1b9 100644 --- a/litex_boards/platforms/crosslink_nx_vip.py +++ b/litex_boards/platforms/crosslink_nx_vip.py @@ -119,17 +119,18 @@ _io = [ # MIPI camera modules # Note that use of MIPI_DPHY standard for + and LVCMOS12H for - is copied from Lattice PDC + # MIPI pins are unconstrained to work around a Radiant 2.0 bug ("camera", 0, - Subsignal("clkp", Pins("A2"), IOStandard("MIPI_DPHY")), - Subsignal("clkn", Pins("B1"), IOStandard("LVCMOS12H")), - Subsignal("dp", Pins("B2 A3 C2 A4"), IOStandard("MIPI_DPHY")), - Subsignal("dn", Pins("C1 B3 D1 B4"), IOStandard("LVCMOS12H")), + Subsignal("clkp", Pins("X")), + Subsignal("clkn", Pins("X")), + Subsignal("dp", Pins("X X X X")), + Subsignal("dn", Pins("X X X X")), ), ("camera", 1, - Subsignal("clkp", Pins("A8"), IOStandard("MIPI_DPHY")), - Subsignal("clkn", Pins("B8"), IOStandard("LVCMOS12H")), - Subsignal("dp", Pins("A7 A9 A6 A10"), IOStandard("MIPI_DPHY")), - Subsignal("dn", Pins("B7 B9 B6 B10"), IOStandard("LVCMOS12H")), + Subsignal("clkp", Pins("X")), + Subsignal("clkn", Pins("X")), + Subsignal("dp", Pins("X X X X")), + Subsignal("dn", Pins("X X X X")), ), ("camera", 2, Subsignal("clkp", Pins("W11"), IOStandard("MIPI_DPHY")),