From 4a18951651bd8daed00312d01a85ec90989d2758 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 1 Sep 2021 08:50:56 +0200 Subject: [PATCH] tul_pynq_z2: Fix copyrights, remove PS7 part for now. --- litex_boards/platforms/tul_pynq_z2.py | 2 +- litex_boards/targets/tul_pynq_z2.py | 17 +++-------------- 2 files changed, 4 insertions(+), 15 deletions(-) diff --git a/litex_boards/platforms/tul_pynq_z2.py b/litex_boards/platforms/tul_pynq_z2.py index e0c9959..61b763f 100644 --- a/litex_boards/platforms/tul_pynq_z2.py +++ b/litex_boards/platforms/tul_pynq_z2.py @@ -1,7 +1,7 @@ # # This file is part of LiteX-Boards. # -# Copyright (c) 2019-2020 Florent Kermarrec +# Copyright (c) 2021 Martin Troiber # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * diff --git a/litex_boards/targets/tul_pynq_z2.py b/litex_boards/targets/tul_pynq_z2.py index e383028..f6ce3cd 100755 --- a/litex_boards/targets/tul_pynq_z2.py +++ b/litex_boards/targets/tul_pynq_z2.py @@ -3,7 +3,8 @@ # # This file is part of LiteX-Boards. # -# Copyright (c) 2019-2020 Florent Kermarrec , +# Copyright (c) 2021 Martin Troiber +# Copyright (c) 2019-2020 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause import os @@ -58,19 +59,7 @@ class BaseSoC(SoCCore): # Zynq7000 Integration --------------------------------------------------------------------- if kwargs.get("cpu_type", None) == "zynq7000": - # Get and set the pre-generated .xci FIXME: change location? add it to the repository? - os.system("wget https://github.com/litex-hub/litex-boards/files/4967144/zybo_z7_ps7.txt") - os.makedirs("xci", exist_ok=True) - os.system("mv zybo_z7_ps7.txt xci/zybo_z7_ps7.xci") - self.cpu.set_ps7_xci("xci/zybo_z7_ps7.xci") - - # Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one) - wb_gp0 = wishbone.Interface() - self.submodules += axi.AXI2Wishbone( - axi = self.cpu.add_axi_gp_master(), - wishbone = wb_gp0, - base_address = 0x43c00000) - self.add_wb_master(wb_gp0) + raise NotImplementedError # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq)