From 4b6a9b2cf066f5608b11126e5d4b5e802daa3142 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 7 Jan 2022 15:19:23 +0100 Subject: [PATCH] targets/spiflash: Simplify self.cpu.set_reset_address call. --- litex_boards/targets/1bitsquared_icebreaker.py | 4 +--- litex_boards/targets/1bitsquared_icebreaker_bitsy.py | 4 +--- litex_boards/targets/efinix_xyloni_dev_kit.py | 4 +--- litex_boards/targets/kosagi_fomu.py | 4 +--- litex_boards/targets/lattice_ice40up5k_evn.py | 4 +--- litex_boards/targets/muselab_icesugar.py | 4 +--- litex_boards/targets/qwertyembedded_beaglewire.py | 4 +--- litex_boards/targets/sipeed_tang_nano_4k.py | 4 +--- litex_boards/targets/tinyfpga_bx.py | 4 +--- litex_boards/targets/trenz_tec0117.py | 4 +--- 10 files changed, 10 insertions(+), 30 deletions(-) diff --git a/litex_boards/targets/1bitsquared_icebreaker.py b/litex_boards/targets/1bitsquared_icebreaker.py index 2ffc315..7efdc36 100755 --- a/litex_boards/targets/1bitsquared_icebreaker.py +++ b/litex_boards/targets/1bitsquared_icebreaker.py @@ -112,9 +112,7 @@ class BaseSoC(SoCCore): size = 32*kB, linker = True) ) - # Set CPU reset address to ROM. - if hasattr(self.cpu, "set_reset_address"): - self.cpu.set_reset_address(self.bus.regions["rom"].origin) + self.cpu.set_reset_address(self.bus.regions["rom"].origin) # Video ------------------------------------------------------------------------------------ if with_video_terminal: diff --git a/litex_boards/targets/1bitsquared_icebreaker_bitsy.py b/litex_boards/targets/1bitsquared_icebreaker_bitsy.py index 9e6ff0e..9527373 100755 --- a/litex_boards/targets/1bitsquared_icebreaker_bitsy.py +++ b/litex_boards/targets/1bitsquared_icebreaker_bitsy.py @@ -107,9 +107,7 @@ class BaseSoC(SoCCore): size = 32*kB, linker = True) ) - # Set CPU reset address to ROM. - if hasattr(self.cpu, "set_reset_address"): - self.cpu.set_reset_address(self.bus.regions["rom"].origin) + self.cpu.set_reset_address(self.bus.regions["rom"].origin) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/efinix_xyloni_dev_kit.py b/litex_boards/targets/efinix_xyloni_dev_kit.py index 5d1d497..6a26f3a 100755 --- a/litex_boards/targets/efinix_xyloni_dev_kit.py +++ b/litex_boards/targets/efinix_xyloni_dev_kit.py @@ -74,9 +74,7 @@ class BaseSoC(SoCCore): size = 32*kB, linker = True) ) - # Set CPU reset address to ROM. - if hasattr(self.cpu, "set_reset_address"): - self.cpu.set_reset_address(self.bus.regions["rom"].origin) + self.cpu.set_reset_address(self.bus.regions["rom"].origin) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: diff --git a/litex_boards/targets/kosagi_fomu.py b/litex_boards/targets/kosagi_fomu.py index 392c098..751ec2c 100755 --- a/litex_boards/targets/kosagi_fomu.py +++ b/litex_boards/targets/kosagi_fomu.py @@ -125,9 +125,7 @@ class BaseSoC(SoCCore): size = 32*kB, linker = True) ) - # Set CPU reset address to ROM. - if hasattr(self.cpu, "set_reset_address"): - self.cpu.set_reset_address(self.bus.regions["rom"].origin) + self.cpu.set_reset_address(self.bus.regions["rom"].origin) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: diff --git a/litex_boards/targets/lattice_ice40up5k_evn.py b/litex_boards/targets/lattice_ice40up5k_evn.py index 9d67218..1db00a0 100755 --- a/litex_boards/targets/lattice_ice40up5k_evn.py +++ b/litex_boards/targets/lattice_ice40up5k_evn.py @@ -93,9 +93,7 @@ class BaseSoC(SoCCore): size = 32*kB, linker = True) ) - # Set CPU reset address to ROM. - if hasattr(self.cpu, "set_reset_address"): - self.cpu.set_reset_address(self.bus.regions["rom"].origin) + self.cpu.set_reset_address(self.bus.regions["rom"].origin) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: diff --git a/litex_boards/targets/muselab_icesugar.py b/litex_boards/targets/muselab_icesugar.py index 4e863aa..251e561 100755 --- a/litex_boards/targets/muselab_icesugar.py +++ b/litex_boards/targets/muselab_icesugar.py @@ -93,9 +93,7 @@ class BaseSoC(SoCCore): size = 32*kB, linker = True) ) - # Set CPU reset address to ROM. - if hasattr(self.cpu, "set_reset_address"): - self.cpu.set_reset_address(self.bus.regions["rom"].origin) + self.cpu.set_reset_address(self.bus.regions["rom"].origin) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: diff --git a/litex_boards/targets/qwertyembedded_beaglewire.py b/litex_boards/targets/qwertyembedded_beaglewire.py index 89b1bb7..b57f361 100755 --- a/litex_boards/targets/qwertyembedded_beaglewire.py +++ b/litex_boards/targets/qwertyembedded_beaglewire.py @@ -100,9 +100,7 @@ class BaseSoC(SoCCore): size = 32*kB, linker = True) ) - # Set CPU reset address to ROM. - if hasattr(self.cpu, "set_reset_address"): - self.cpu.set_reset_address(self.bus.regions["rom"].origin) + self.cpu.set_reset_address(self.bus.regions["rom"].origin) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( diff --git a/litex_boards/targets/sipeed_tang_nano_4k.py b/litex_boards/targets/sipeed_tang_nano_4k.py index 896aa1f..74b45a3 100755 --- a/litex_boards/targets/sipeed_tang_nano_4k.py +++ b/litex_boards/targets/sipeed_tang_nano_4k.py @@ -101,9 +101,7 @@ class BaseSoC(SoCCore): size = 32*kB, linker = True) ) - # Set CPU reset address to ROM. - if hasattr(self.cpu, "set_reset_address"): - self.cpu.set_reset_address(self.bus.regions["rom"].origin) + self.cpu.set_reset_address(self.bus.regions["rom"].origin) # HyperRAM --------------------------------------------------------------------------------- if with_hyperram: diff --git a/litex_boards/targets/tinyfpga_bx.py b/litex_boards/targets/tinyfpga_bx.py index 6d40bdc..0b6cab9 100755 --- a/litex_boards/targets/tinyfpga_bx.py +++ b/litex_boards/targets/tinyfpga_bx.py @@ -53,9 +53,7 @@ class BaseSoC(SoCCore): size = 32*kB, linker = True) ) - # Set CPU reset address to ROM. - if hasattr(self.cpu, "set_reset_address"): - self.cpu.set_reset_address(self.bus.regions["rom"].origin) + self.cpu.set_reset_address(self.bus.regions["rom"].origin) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: diff --git a/litex_boards/targets/trenz_tec0117.py b/litex_boards/targets/trenz_tec0117.py index b77e659..41bc8d2 100755 --- a/litex_boards/targets/trenz_tec0117.py +++ b/litex_boards/targets/trenz_tec0117.py @@ -87,9 +87,7 @@ class BaseSoC(SoCCore): size = 32*kB, linker = True) ) - # Set CPU reset address to ROM. - if hasattr(self.cpu, "set_reset_address"): - self.cpu.set_reset_address(self.bus.regions["rom"].origin) + self.cpu.set_reset_address(self.bus.regions["rom"].origin) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: