From 4ba57938222bbcfebea612862c9ccb349c82051e Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 4 Nov 2022 10:52:33 +0800 Subject: [PATCH] sitlinv_stlv7325: remove unexistent COL/CRS pins The COL and CRS pins of the Ethernet PHY is not connected on the board at all, but assigned dummy positions in the platform definition, which leads to Vivado warning when building. Remove these pins from the platform definition. Signed-off-by: Icenowy Zheng --- litex_boards/platforms/sitlinv_stlv7325.py | 4 ---- 1 file changed, 4 deletions(-) diff --git a/litex_boards/platforms/sitlinv_stlv7325.py b/litex_boards/platforms/sitlinv_stlv7325.py index ec7a4a5..992ba64 100644 --- a/litex_boards/platforms/sitlinv_stlv7325.py +++ b/litex_boards/platforms/sitlinv_stlv7325.py @@ -164,8 +164,6 @@ _io = [ Subsignal("tx_en", Pins("F12")), Subsignal("tx_er", Pins("E13")), Subsignal("tx_data", Pins("G12 E11 G11 C14 D14 C13 C11 D13")), - Subsignal("col", Pins("W19")), - Subsignal("crs", Pins("R30")), IOStandard("LVCMOS15") ), ("eth", 1, @@ -179,8 +177,6 @@ _io = [ Subsignal("tx_en", Pins("F8")), Subsignal("tx_er", Pins("D9")), Subsignal("tx_data", Pins("H11 J11 H9 J10 H12 F10 G10 F9")), - Subsignal("col", Pins("W19")), - Subsignal("crs", Pins("R30")), IOStandard("LVCMOS15") ),