qmtech_wukong: Change --board-version to --revision as on other boards.
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@ -223,7 +223,7 @@ class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self, board_version=1, speedgrade=-2, toolchain="vivado"):
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def __init__(self, revision=1, speedgrade=-2, toolchain="vivado"):
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# Check Speedgrade.
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if speedgrade not in [-1,-2]:
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raise ValueError(f"Speedgrade {speedgrade} unsupported.")
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@ -233,7 +233,7 @@ class Platform(Xilinx7SeriesPlatform):
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1 : _io_v1,
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2 : _io_v2,
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3 : _io_v3,
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}[board_version])
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}[revision])
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# Create Platform.
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Xilinx7SeriesPlatform.__init__(self, f"xc7a100t{speedgrade}fgg676", io, _connectors, toolchain=toolchain)
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@ -244,7 +244,7 @@ class Platform(Xilinx7SeriesPlatform):
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 16]")
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if board_version == 1:
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if revision == 1:
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self.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk50_IBUF]")
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self.add_platform_command("set_property CFGBVS VCCO [current_design]")
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self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")
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@ -74,7 +74,7 @@ class _CRG(LiteXModule):
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=125e6, board_version=1, speedgrade=-2,
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def __init__(self, sys_clk_freq=100e6, revision=1, speedgrade=-2,
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with_ethernet = False,
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with_etherbone = False,
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eth_ip = "192.168.1.50",
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@ -83,7 +83,7 @@ class BaseSoC(SoCCore):
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with_video_framebuffer = False,
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video_timing = "640x480@60Hz",
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**kwargs):
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platform = qmtech_wukong.Platform(board_version=board_version,speedgrade=speedgrade)
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platform = qmtech_wukong.Platform(revision=revision,speedgrade=speedgrade)
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# CRG --------------------------------------------------------------------------------------
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with_video_pll = (with_video_terminal or with_video_framebuffer)
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@ -93,7 +93,7 @@ class BaseSoC(SoCCore):
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)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident=f"LiteX SoC on QMTECH Wukong Board V{board_version}", **kwargs)
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SoCCore.__init__(self, platform, sys_clk_freq, ident=f"LiteX SoC on QMTECH Wukong Board V{revision}", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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@ -138,8 +138,8 @@ def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=qmtech_wukong.Platform, description="LiteX SoC on QMTECH Wukong Board.")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--board-version", default=1, help="Board version (1 , 2 or 3).")
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parser.add_target_argument("--speedgrade", default=-1, help="FPGA speedgrade (-1 or -2).")
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parser.add_target_argument("--revision", default=1, help="Board version (1 , 2 or 3).")
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parser.add_target_argument("--speedgrade", default=-1, type=int, help="FPGA speedgrade (-1 or -2).")
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ethopts = parser.target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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@ -154,7 +154,7 @@ def main():
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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board_version = int(args.board_version),
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revision = int(args.revision),
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speedgrade = args.speedgrade,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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@ -167,7 +167,7 @@ def main():
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soc.platform.add_extension(qmtech_wukong._sdcard_pmod_io)
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soc.add_spi_sdcard()
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if args.with_sdcard:
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if int(args.board_version) == 1:
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if int(args.revision) == 1:
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soc.platform.add_extension(qmtech_wukong._sdcard_pmod_io)
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soc.add_sdcard()
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