diff --git a/litex_boards/targets/digilent_arty.py b/litex_boards/targets/digilent_arty.py index 5032cd1..11bbaaf 100755 --- a/litex_boards/targets/digilent_arty.py +++ b/litex_boards/targets/digilent_arty.py @@ -30,7 +30,7 @@ from liteeth.phy.mii import LiteEthPHYMII # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): - def __init__(self, platform, sys_clk_freq, with_mapped_flash=False): + def __init__(self, platform, sys_clk_freq): self.rst = Signal() self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) @@ -60,7 +60,7 @@ class BaseSoC(SoCCore): def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, ident_version=True, with_led_chaser=True, with_jtagbone=True, - with_mapped_flash=False, with_pmod_gpio=False, **kwargs): + with_spi_flash=False, with_pmod_gpio=False, **kwargs): platform = arty.Platform(variant=variant, toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- @@ -70,7 +70,7 @@ class BaseSoC(SoCCore): **kwargs) # CRG -------------------------------------------------------------------------------------- - self.submodules.crg = _CRG(platform, sys_clk_freq, with_mapped_flash) + self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: @@ -99,7 +99,7 @@ class BaseSoC(SoCCore): self.add_jtagbone() # SPI Flash -------------------------------------------------------------------------------- - if with_mapped_flash: + if with_spi_flash: from litespi.modules import S25FL128L from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="4x", module=S25FL128L(Codes.READ_1_1_4), with_master=True) @@ -135,7 +135,7 @@ def main(): parser.add_argument("--sdcard-adapter", type=str, help="SDCard PMOD adapter: digilent (default) or numato") parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output") parser.add_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support") - parser.add_argument("--with-mapped-flash", action="store_true", help="Enable Memory Mapped Flash") + parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)") parser.add_argument("--with-pmod-gpio", action="store_true", help="Enable GPIOs through PMOD") # FIXME: Temporary test. builder_args(parser) soc_core_args(parser) @@ -145,17 +145,17 @@ def main(): assert not (args.with_etherbone and args.eth_dynamic_ip) soc = BaseSoC( - variant = args.variant, - toolchain = args.toolchain, - sys_clk_freq = int(float(args.sys_clk_freq)), - with_ethernet = args.with_ethernet, - with_etherbone = args.with_etherbone, - eth_ip = args.eth_ip, - eth_dynamic_ip = args.eth_dynamic_ip, - ident_version = args.no_ident_version, - with_jtagbone = args.with_jtagbone, - with_mapped_flash = args.with_mapped_flash, - with_pmod_gpio = args.with_pmod_gpio, + variant = args.variant, + toolchain = args.toolchain, + sys_clk_freq = int(float(args.sys_clk_freq)), + with_ethernet = args.with_ethernet, + with_etherbone = args.with_etherbone, + eth_ip = args.eth_ip, + eth_dynamic_ip = args.eth_dynamic_ip, + ident_version = args.no_ident_version, + with_jtagbone = args.with_jtagbone, + with_spi_flash = args.with_spi_flash, + with_pmod_gpio = args.with_pmod_gpio, **soc_core_argdict(args) ) if args.sdcard_adapter == "numato": @@ -166,6 +166,7 @@ def main(): soc.add_spi_sdcard() if args.with_sdcard: soc.add_sdcard() + builder = Builder(soc, **builder_argdict(args)) builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {} builder.build(**builder_kwargs, run=args.build) diff --git a/litex_boards/targets/qmtech_xc7a35t.py b/litex_boards/targets/qmtech_xc7a35t.py index ce3f4b7..e7f9fb4 100755 --- a/litex_boards/targets/qmtech_xc7a35t.py +++ b/litex_boards/targets/qmtech_xc7a35t.py @@ -72,7 +72,7 @@ class BaseSoC(SoCCore): def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_daughterboard=False, with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, - ident_version=True, with_jtagbone=True, with_mapped_flash=False, **kwargs): + ident_version=True, with_jtagbone=True, with_spi_flash=False, **kwargs): platform = qmtech_xc7a35t.Platform(toolchain=toolchain, with_daughterboard=with_daughterboard) # SoCCore ---------------------------------------------------------------------------------- @@ -113,7 +113,7 @@ class BaseSoC(SoCCore): self.add_jtagbone() # SPI Flash -------------------------------------------------------------------------------- - if with_mapped_flash: + if with_spi_flash: from litespi.modules import MT25QL128 from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="4x", module=MT25QL128(Codes.READ_1_1_1), with_master=True) @@ -154,7 +154,7 @@ def main(): sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output") parser.add_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support") - parser.add_argument("--with-mapped-flash", action="store_true", help="Enable Memory Mapped Flash") + parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)") viopts = parser.add_mutually_exclusive_group() viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)") viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA)") @@ -173,7 +173,7 @@ def main(): eth_dynamic_ip = args.eth_dynamic_ip, ident_version = args.no_ident_version, with_jtagbone = args.with_jtagbone, - with_mapped_flash = args.with_mapped_flash, + with_spi_flash = args.with_spi_flash, with_video_terminal = args.with_video_terminal, with_video_framebuffer = args.with_video_framebuffer, **soc_core_argdict(args)