From 4edf196911149b22c8a8ea2e1e249f923c4cd243 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 11 Feb 2020 17:45:35 +0100 Subject: [PATCH] targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC) --- litex_boards/targets/ac701.py | 2 +- litex_boards/targets/arty.py | 2 +- litex_boards/targets/c10lprefkit.py | 2 +- litex_boards/targets/kc705.py | 2 +- litex_boards/targets/kcu105.py | 2 +- litex_boards/targets/linsn_rv901t.py | 2 +- litex_boards/targets/mimas_a7.py | 2 +- litex_boards/targets/netv2.py | 2 +- litex_boards/targets/nexys4ddr.py | 2 +- litex_boards/targets/simple.py | 2 +- litex_boards/targets/trellisboard.py | 2 +- litex_boards/targets/versa_ecp5.py | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) diff --git a/litex_boards/targets/ac701.py b/litex_boards/targets/ac701.py index 4bea97f..e6342c1 100755 --- a/litex_boards/targets/ac701.py +++ b/litex_boards/targets/ac701.py @@ -131,8 +131,8 @@ class EthernetSoC(BaseSoC): dw = 32, interface = "wishbone", endianness = self.cpu.endianness) - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/targets/arty.py b/litex_boards/targets/arty.py index 7ec6afb..a822f93 100755 --- a/litex_boards/targets/arty.py +++ b/litex_boards/targets/arty.py @@ -94,8 +94,8 @@ class EthernetSoC(BaseSoC): dw = 32, interface = "wishbone", endianness = self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex_boards/targets/c10lprefkit.py b/litex_boards/targets/c10lprefkit.py index 761f25d..08d5dde 100755 --- a/litex_boards/targets/c10lprefkit.py +++ b/litex_boards/targets/c10lprefkit.py @@ -135,8 +135,8 @@ class EthernetSoC(BaseSoC): dw = 32, interface = "wishbone", endianness = self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex_boards/targets/kc705.py b/litex_boards/targets/kc705.py index 24ccf54..10624ec 100755 --- a/litex_boards/targets/kc705.py +++ b/litex_boards/targets/kc705.py @@ -88,8 +88,8 @@ class EthernetSoC(BaseSoC): dw = 32, interface = "wishbone", endianness = self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py index f116d00..f14394f 100755 --- a/litex_boards/targets/kcu105.py +++ b/litex_boards/targets/kcu105.py @@ -123,8 +123,8 @@ class EthernetSoC(BaseSoC): dw = 32, interface = "wishbone", endianness = self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex_boards/targets/linsn_rv901t.py b/litex_boards/targets/linsn_rv901t.py index 86e78e6..e1d6e13 100755 --- a/litex_boards/targets/linsn_rv901t.py +++ b/litex_boards/targets/linsn_rv901t.py @@ -84,8 +84,8 @@ class EthernetSoC(BaseSoC): dw = 32, interface = "wishbone", endianness = self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex_boards/targets/mimas_a7.py b/litex_boards/targets/mimas_a7.py index cc2a085..30c422b 100755 --- a/litex_boards/targets/mimas_a7.py +++ b/litex_boards/targets/mimas_a7.py @@ -86,8 +86,8 @@ class EthernetSoC(BaseSoC): # mac self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex_boards/targets/netv2.py b/litex_boards/targets/netv2.py index 57c5196..94d2750 100755 --- a/litex_boards/targets/netv2.py +++ b/litex_boards/targets/netv2.py @@ -90,8 +90,8 @@ class EthernetSoC(BaseSoC): dw = 32, interface = "wishbone", endianness = self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex_boards/targets/nexys4ddr.py b/litex_boards/targets/nexys4ddr.py index 3796bb4..a4a9e85 100755 --- a/litex_boards/targets/nexys4ddr.py +++ b/litex_boards/targets/nexys4ddr.py @@ -89,8 +89,8 @@ class EthernetSoC(BaseSoC): dw = 32, interface = "wishbone", endianness = self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex_boards/targets/simple.py b/litex_boards/targets/simple.py index fa74077..7250c98 100755 --- a/litex_boards/targets/simple.py +++ b/litex_boards/targets/simple.py @@ -48,8 +48,8 @@ class EthernetSoC(BaseSoC): # mac self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index ac3f22b..dcd29e2 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -120,8 +120,8 @@ class EthernetSoC(BaseSoC): # mac self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index 29b1f88..29d8ef3 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -114,8 +114,8 @@ class EthernetSoC(BaseSoC): # mac self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints