From 2d2a10621f59052b56543865afd2b638876fdda2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Fri, 23 Apr 2021 15:25:47 +0200 Subject: [PATCH 1/7] antmicro_lpddr4_test_board: fix ethernet rx delay issue --- litex_boards/targets/antmicro_lpddr4_test_board.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/litex_boards/targets/antmicro_lpddr4_test_board.py b/litex_boards/targets/antmicro_lpddr4_test_board.py index cf63b97..7b46f9e 100755 --- a/litex_boards/targets/antmicro_lpddr4_test_board.py +++ b/litex_boards/targets/antmicro_lpddr4_test_board.py @@ -91,9 +91,14 @@ class BaseSoC(SoCCore): # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: + # Traces between PHY and FPGA introduce ignorable delays of ~0.165ns +/- 0.015ns. + # PHY chip does not introduce delays on TX (FPGA->PHY), however it includes 1.2ns + # delay for RX CLK so we only need 0.8ns to match the desired 2ns. self.submodules.ethphy = LiteEthS7PHYRGMII( clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth")) + pads = self.platform.request("eth"), + rx_delay = 0.8e-9, + ) if with_ethernet: self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) if with_etherbone: From 694608688db01b5efcd9f6e99c89911eec21c3f0 Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Tue, 27 Apr 2021 08:52:11 +0700 Subject: [PATCH 2/7] terasic_sockit: fix: make video clock also optional as video terminal is optional --- litex_boards/targets/terasic_sockit.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/litex_boards/targets/terasic_sockit.py b/litex_boards/targets/terasic_sockit.py index 1a99868..b9c7599 100755 --- a/litex_boards/targets/terasic_sockit.py +++ b/litex_boards/targets/terasic_sockit.py @@ -67,11 +67,12 @@ class W9825G6KH6(SDRModule): # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): - def __init__(self, platform, sys_clk_freq, with_sdram=False, sdram_rate="1:2"): + def __init__(self, platform, sys_clk_freq, with_sdram=False, sdram_rate="1:2", with_video_terminal=False): self.sdram_rate = sdram_rate self.rst = Signal() self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_vga = ClockDomain(reset_less=True) + if with_video_terminal: + self.clock_domains.cd_vga = ClockDomain(reset_less=True) if with_sdram: if sdram_rate == "1:2": self.clock_domains.cd_sys2x = ClockDomain() @@ -87,7 +88,10 @@ class _CRG(Module): self.comb += pll.reset.eq(self.rst) pll.register_clkin(clk50, 50e6) pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_vga, 65e6) + + if with_video_terminal: + pll.create_clkout(self.cd_vga, 65e6) + if with_sdram: if sdram_rate == "1:2": pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) @@ -117,7 +121,7 @@ class BaseSoC(SoCCore): **kwargs) # CRG -------------------------------------------------------------------------------------- - self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=mister_sdram != None, sdram_rate=sdram_rate) + self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=mister_sdram != None, sdram_rate=sdram_rate, with_video_terminal=with_video_terminal) # SDR SDRAM -------------------------------------------------------------------------------- if mister_sdram is not None: From cfbcb8538df1172b597fdcabd60788a3adc3b0f1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 28 Apr 2021 16:59:09 +0200 Subject: [PATCH 3/7] siglent_sds1104xe: Use custom 800x480 video timings. --- litex_boards/targets/siglent_sds1104xe.py | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/siglent_sds1104xe.py b/litex_boards/targets/siglent_sds1104xe.py index dbfafe1..ba1c916 100755 --- a/litex_boards/targets/siglent_sds1104xe.py +++ b/litex_boards/targets/siglent_sds1104xe.py @@ -144,12 +144,23 @@ class BaseSoC(SoCCore): self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk) # Video ------------------------------------------------------------------------------------ + video_timings = ("800x480@60Hz", { + "pix_clk" : 40e6, + "h_active" : 800, + "h_blanking" : 256, + "h_sync_offset" : 40, + "h_sync_width" : 128, + "v_active" : 480, + "v_blanking" : 28, + "v_sync_offset" : 1, + "v_sync_width" : 4, + }) if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoDVIPHY(platform.request("lcd"), clock_domain="dvi") if with_video_terminal: - self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="dvi") + self.add_video_terminal(phy=self.videophy, timings=video_timings, clock_domain="dvi") if with_video_framebuffer: - self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="dvi") + self.add_video_framebuffer(phy=self.videophy, timings=video_timings, clock_domain="dvi") # Build -------------------------------------------------------------------------------------------- From 7d651a9a1736ddada923eba28881a3c91ee100bd Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 29 Apr 2021 10:41:19 +0200 Subject: [PATCH 4/7] siglent_sds1104xe: Switch to VideoVGAPHY and adjust timings. --- litex_boards/platforms/siglent_sds1104xe.py | 12 ++++++------ litex_boards/targets/siglent_sds1104xe.py | 18 +++++++++--------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/litex_boards/platforms/siglent_sds1104xe.py b/litex_boards/platforms/siglent_sds1104xe.py index bdeaba3..382b879 100644 --- a/litex_boards/platforms/siglent_sds1104xe.py +++ b/litex_boards/platforms/siglent_sds1104xe.py @@ -36,12 +36,12 @@ _io = [ # Documented by https://github.com/360nosc0pe project. # LCD ("lcd", 0, - Subsignal("clk", Pins("D20")), - Subsignal("vsync", Pins("A21")), - Subsignal("hsync", Pins("A22")), - Subsignal("r", Pins("D22 D21 C22 C20 B22 B21")), - Subsignal("g", Pins("F16 E21 E20 E19 E18 E16")), - Subsignal("b", Pins("G22 F22 F21 F19 F18 F17")), + Subsignal("clk", Pins("D20")), + Subsignal("vsync_n", Pins("A21")), + Subsignal("hsync_n", Pins("A22")), + Subsignal("r", Pins("D22 D21 C22 C20 B22 B21")), + Subsignal("g", Pins("F16 E21 E20 E19 E18 E16")), + Subsignal("b", Pins("G22 F22 F21 F19 F18 F17")), IOStandard("LVCMOS33"), ), diff --git a/litex_boards/targets/siglent_sds1104xe.py b/litex_boards/targets/siglent_sds1104xe.py index ba1c916..d86b13a 100755 --- a/litex_boards/targets/siglent_sds1104xe.py +++ b/litex_boards/targets/siglent_sds1104xe.py @@ -29,7 +29,7 @@ from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * -from litex.soc.cores.video import VideoDVIPHY +from litex.soc.cores.video import VideoVGAPHY from litedram.modules import MT41K64M16 from litedram.phy import s7ddrphy @@ -59,7 +59,7 @@ class _CRG(Module): pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) pll.create_clkout(self.cd_idelay, 200e6) - pll.create_clkout(self.cd_dvi, 40e6) + pll.create_clkout(self.cd_dvi, 33.3e6) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) @@ -145,18 +145,18 @@ class BaseSoC(SoCCore): # Video ------------------------------------------------------------------------------------ video_timings = ("800x480@60Hz", { - "pix_clk" : 40e6, + "pix_clk" : 33.3e6, "h_active" : 800, "h_blanking" : 256, - "h_sync_offset" : 40, - "h_sync_width" : 128, + "h_sync_offset" : 210, + "h_sync_width" : 1, "v_active" : 480, - "v_blanking" : 28, - "v_sync_offset" : 1, - "v_sync_width" : 4, + "v_blanking" : 45, + "v_sync_offset" : 22, + "v_sync_width" : 1, }) if with_video_terminal or with_video_framebuffer: - self.submodules.videophy = VideoDVIPHY(platform.request("lcd"), clock_domain="dvi") + self.submodules.videophy = VideoVGAPHY(platform.request("lcd"), clock_domain="dvi") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings=video_timings, clock_domain="dvi") if with_video_framebuffer: From c28a16139265a337a398a6ea1b2e41abb2a121f7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 29 Apr 2021 11:02:13 +0200 Subject: [PATCH 5/7] siglent_sds1104xe: Expose ethphy (to allow correct .dts generation). --- litex_boards/targets/siglent_sds1104xe.py | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/litex_boards/targets/siglent_sds1104xe.py b/litex_boards/targets/siglent_sds1104xe.py index d86b13a..9c20c78 100755 --- a/litex_boards/targets/siglent_sds1104xe.py +++ b/litex_boards/targets/siglent_sds1104xe.py @@ -107,15 +107,14 @@ class BaseSoC(SoCCore): from liteeth.frontend.etherbone import LiteEthEtherbone # Ethernet PHY - ethphy = LiteEthPHYMII( + self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) - self.submodules += ethphy etherbone_ip_address = convert_ip("192.168.1.51") etherbone_mac_address = 0x10e2d5000001 # Ethernet MAC - self.submodules.ethmac = LiteEthMAC(phy=ethphy, dw=8, + self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=8, interface = "hybrid", endianness = self.cpu.endianness, hw_mac = etherbone_mac_address) @@ -137,10 +136,10 @@ class BaseSoC(SoCCore): self.add_wb_master(self.etherbone.wishbone.bus) # Timing constraints - eth_rx_clk = ethphy.crg.cd_eth_rx.clk - eth_tx_clk = ethphy.crg.cd_eth_tx.clk - self.platform.add_period_constraint(eth_rx_clk, 1e9/ethphy.rx_clk_freq) - self.platform.add_period_constraint(eth_tx_clk, 1e9/ethphy.tx_clk_freq) + eth_rx_clk = self.ethphy.crg.cd_eth_rx.clk + eth_tx_clk = self.ethphy.crg.cd_eth_tx.clk + self.platform.add_period_constraint(eth_rx_clk, 1e9/self.ethphy.rx_clk_freq) + self.platform.add_period_constraint(eth_tx_clk, 1e9/self.ethphy.tx_clk_freq) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk) # Video ------------------------------------------------------------------------------------ From 6117b98049ab4f90e522deb16488eb79b3206571 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 29 Apr 2021 11:52:41 +0200 Subject: [PATCH 6/7] siglent_sds1104xe: Avoid disabling hardware interface with BIOS ethernet reset. --- litex_boards/targets/siglent_sds1104xe.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex_boards/targets/siglent_sds1104xe.py b/litex_boards/targets/siglent_sds1104xe.py index 9c20c78..e7e9bf1 100755 --- a/litex_boards/targets/siglent_sds1104xe.py +++ b/litex_boards/targets/siglent_sds1104xe.py @@ -130,6 +130,7 @@ class BaseSoC(SoCCore): self.submodules.ip = LiteEthIP(self.ethmac, etherbone_mac_address, etherbone_ip_address, self.arp.table, dw=8) self.submodules.icmp = LiteEthICMP(self.ip, etherbone_ip_address, dw=8) self.submodules.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=8) + self.add_constant("ETH_PHY_NO_RESET") # Disable reset from BIOS to avoid disabling Hardware Interface. # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master") From 9686db0ed3c323bb2e455930b2387dcfd0e54330 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 29 Apr 2021 11:56:52 +0200 Subject: [PATCH 7/7] targets: Update names in build descriptions. --- litex_boards/targets/siglent_sds1104xe.py | 2 +- litex_boards/targets/sqrl_acorn.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/siglent_sds1104xe.py b/litex_boards/targets/siglent_sds1104xe.py index e7e9bf1..8e72374 100755 --- a/litex_boards/targets/siglent_sds1104xe.py +++ b/litex_boards/targets/siglent_sds1104xe.py @@ -8,7 +8,7 @@ # Build/Use ---------------------------------------------------------------------------------------- # Build/Load bitstream: -# ./sds1104xe.py --with-etherbone --uart-name=crossover --csr-csv=csr.csv --build --load +# ./siglent_ds1104xe.py --with-etherbone --uart-name=crossover --csr-csv=csr.csv --build --load # # Test Ethernet: # ping 192.168.1.50 diff --git a/litex_boards/targets/sqrl_acorn.py b/litex_boards/targets/sqrl_acorn.py index 2840691..4a9ddd0 100755 --- a/litex_boards/targets/sqrl_acorn.py +++ b/litex_boards/targets/sqrl_acorn.py @@ -8,7 +8,7 @@ # Build/Use ---------------------------------------------------------------------------------------- # Build/Load bitstream: -# ./acorn_cle.py --uart-name=crossover --with-pcie --build --driver --load (or --flash) +# ./sqrl_acorn.py --uart-name=crossover --with-pcie --build --driver --load (or --flash) # #.Build the kernel and load it: # cd build//driver/kernel