From 3a6a9258cef17e31cfdefbaaac23a2cfc9f25560 Mon Sep 17 00:00:00 2001 From: Paul Sajna Date: Sat, 25 Jan 2020 03:00:57 -0800 Subject: [PATCH 1/4] add de10 nano board add iostandard to hdmi --- litex_boards/community/platforms/de10nano.py | 100 +++++++++++++++++++ litex_boards/community/targets/de10nano.py | 94 +++++++++++++++++ 2 files changed, 194 insertions(+) create mode 100644 litex_boards/community/platforms/de10nano.py create mode 100755 litex_boards/community/targets/de10nano.py diff --git a/litex_boards/community/platforms/de10nano.py b/litex_boards/community/platforms/de10nano.py new file mode 100644 index 0000000..0aa76d5 --- /dev/null +++ b/litex_boards/community/platforms/de10nano.py @@ -0,0 +1,100 @@ +# This file is Copyright (c) 2014-2019 Florent Kermarrec +# License: BSD + +from litex.build.generic_platform import * +from litex.build.altera import AlteraPlatform +from litex.build.altera.programmer import USBBlaster + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + ("clk50", 0, Pins("V11"), IOStandard("3.3-V LVTTL")), + ("clk50", 1, Pins("Y13"), IOStandard("3.3-V LVTTL")), + ("clk50", 2, Pins("E11"), IOStandard("3.3-V LVTTL")), + + ("user_led", 0, Pins("W15"), IOStandard("3.3-V LVTTL")), + ("user_led", 1, Pins("AA24"), IOStandard("3.3-V LVTTL")), + ("user_led", 2, Pins("V16"), IOStandard("3.3-V LVTTL")), + ("user_led", 3, Pins("V15"), IOStandard("3.3-V LVTTL")), + ("user_led", 4, Pins("AF26"), IOStandard("3.3-V LVTTL")), + ("user_led", 5, Pins("AE26"), IOStandard("3.3-V LVTTL")), + + ("key", 0, Pins("AH17"), IOStandard("3.3-V LVTTL")), + ("key", 1, Pins("AH16"), IOStandard("3.3-V LVTTL")), + + ("sw", 0, Pins("Y24"), IOStandard("3.3-V LVTTL")), + ("sw", 1, Pins("W24"), IOStandard("3.3-V LVTTL")), + ("sw", 2, Pins("W21"), IOStandard("3.3-V LVTTL")), + ("sw", 3, Pins("W20"), IOStandard("3.3-V LVTTL")), + + ("serial", 0, + Subsignal("tx", Pins("AF13"), IOStandard("3.3-V LVTTL")), # Arduino_IO1 + Subsignal("rx", Pins("AG13"), IOStandard("3.3-V LVTTL")) # Arduino_IO0 + ), + + + + ("g_sensor", 0, + Subsignal("int", Pins("A17")), + Subsignal("sclk", Pins("C18")), + Subsignal("sdat", Pins("A19")), + IOStandard("3.3-V LVTTL") + ), + + ("adc", 0, + Subsignal("convst", Pins("U9")), + Subsignal("sclk", Pins("V10")), + Subsignal("sdi", Pins("AC4")), + Subsignal("sdo", Pins("AD4")), + IOStandard("3.3-V LVTTL") + ), + + ("hdmi", 0, + Subsignal("tx_d_r", Pins("AS12 AE12 W8 Y8 AD11 AD10 AE11 Y5")), + Subsignal("tx_d_g", Pins("AF10 Y4 AE9 AB4 AE7 AF6 AF8 AF5")), + Subsignal("tx_d_b", Pins("AE4 AH2 AH4 AH5 AH6 AG6 AF9 AE8")), + Subsignal("tx_clk", Pins("AG5")), + Subsignal("tx_de", Pins("AD19")), + Subsignal("tx_hs", Pins("T8")), + Subsignal("tx_vs", Pins("V13")), + Subsignal("tx_int", Pins("AF11")), + Subsignal("i2s0", Pins("T13")), + Subsignal("mclk", Pins("U11")), + Subsignal("lrclk", Pins("T11")), + Subsignal("sclk", Pins("T12")), + Subsignal("scl", Pins("U10")), + Subsignal("sda", Pins("AA4")), + IOStandard("3.3-V LVTTL") + ), + + ("gpio_0", 0, + Pins("V12 E8 W12 D11 D8 AH13 AF7 AH14 AF4 AH3 AD5 AG14 AE23 D12 AD20", + "C12 AD17 AC23 AC22 Y19 AB23 AA19 W11 AA18 W14 Y18 Y17 AB25 AB26", + "Y11 AA26 AA13 AA11"), + IOStandard("3.3-V LVTTL") + ), + ("gpio_1", 0, + Pins("Y15 AC24 AA15 AD26 AG28 AF28 AE25 AF27 AG26 AH27 AG25 AH26 AH24", + "AF25 AG23 AF24 AG24 AH22 AH21 AG21 AH23 AA20 AF22 AE22 AG20 AF21", + "AH23 AA20 AF22 AE22 AG20 AF21 AG19 AH19 AG18 AH18 AF18 AF20 AG15", + "AE20 AE19 AE17"), + IOStandard("3.3-V LVTTL") + ), + ("arduino", 0, + Pins("AG13 AF13 AG10 AG9 U14 U13 AG8 AH8 AF17 AE15 AF15 AG16 AH11 AH12", + "AH9, AG11, AH7"), + IOStandard("3.3-V LVTTL") + ), +] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(AlteraPlatform): + default_clk_name = "clk50" + default_clk_period = 1e9/50e6 + + def __init__(self): + AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io) + + def create_programmer(self): + return USBBlaster() diff --git a/litex_boards/community/targets/de10nano.py b/litex_boards/community/targets/de10nano.py new file mode 100755 index 0000000..f408984 --- /dev/null +++ b/litex_boards/community/targets/de10nano.py @@ -0,0 +1,94 @@ +#!/usr/bin/env python3 + +# This file is Copyright (c) 2015-2019 Florent Kermarrec +# License: BSD + +import argparse + +from migen import * +from migen.genlib.resetsync import AsyncResetSynchronizer + +from litex_boards.platforms import de10nano + +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * + + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(Module): + def __init__(self, platform): + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys_ps = ClockDomain() + + # # # + + # Clk / Rst + clk50 = platform.request("clk50") + platform.add_period_constraint(clk50, 1e9/50e6) + + # PLL + pll_locked = Signal() + pll_clk_out = Signal(6) + self.specials += \ + Instance("ALTPLL", + p_BANDWIDTH_TYPE = "AUTO", + p_CLK0_DIVIDE_BY = 1, + p_CLK0_DUTY_CYCLE = 50, + p_CLK0_MULTIPLY_BY = 1, + p_CLK0_PHASE_SHIFT = "0", + p_CLK1_DIVIDE_BY = 1, + p_CLK1_DUTY_CYCLE = 50, + p_CLK1_MULTIPLY_BY = 1, + p_CLK1_PHASE_SHIFT = "-10000", + p_COMPENSATE_CLOCK = "CLK0", + p_INCLK0_INPUT_FREQUENCY = 20000, + p_OPERATION_MODE = "NORMAL", + i_INCLK = clk50, + o_CLK = pll_clk_out, + i_ARESET = 0, + i_CLKENA = 0x3f, + i_EXTCLKENA = 0xf, + i_FBIN = 1, + i_PFDENA = 1, + i_PLLENA = 1, + o_LOCKED = pll_locked, + ) + self.comb += [ + self.cd_sys.clk.eq(pll_clk_out[0]), + self.cd_sys_ps.clk.eq(pll_clk_out[1]), + ] + self.specials += [ + AsyncResetSynchronizer(self.cd_sys, ~pll_locked), + AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked) + ] + + +# BaseSoC ------------------------------------------------------------------------------------------ + +class BaseSoC(SoCCore): + def __init__(self, sys_clk_freq=int(50e6), **kwargs): + assert sys_clk_freq == int(50e6) + platform = de10nano.Platform() + + # SoCSDRAM --------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform) + +# Build -------------------------------------------------------------------------------------------- + +def main(): + parser = argparse.ArgumentParser(description="LiteX SoC on DE10 Nano") + builder_args(parser) + soc_core_args(parser) + args = parser.parse_args() + + soc = BaseSoC(**soc_core_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + builder.build() + + +if __name__ == "__main__": + main() From 5091a1b40af2febca4c636e21f32589e52a0608c Mon Sep 17 00:00:00 2001 From: Paul Sajna Date: Wed, 29 Jan 2020 13:59:57 -0800 Subject: [PATCH 2/4] WIP sdram module option --- litex_boards/community/platforms/de10nano.py | 25 ++++++++++-- litex_boards/community/targets/de10nano.py | 40 ++++++++++++++++++-- 2 files changed, 59 insertions(+), 6 deletions(-) diff --git a/litex_boards/community/platforms/de10nano.py b/litex_boards/community/platforms/de10nano.py index 0aa76d5..162bae0 100644 --- a/litex_boards/community/platforms/de10nano.py +++ b/litex_boards/community/platforms/de10nano.py @@ -32,8 +32,6 @@ _io = [ Subsignal("rx", Pins("AG13"), IOStandard("3.3-V LVTTL")) # Arduino_IO0 ), - - ("g_sensor", 0, Subsignal("int", Pins("A17")), Subsignal("sclk", Pins("C18")), @@ -87,6 +85,26 @@ _io = [ ), ] +_mister_sdram_module_io = [ + ("sdram_clock", 0, Pins("AD20"), IOStandard("3.3-V LVTTL")), + ("sdram", 0, + Subsignal("cke", Pins("AG10")), + Subsignal("a", Pins( + "Y11 AA26 AA13 AA11 W11 Y19 AB23 AC23 AC22 C12 AB26 AD17 D12")), + Subsignal("dq", Pins( + "E8 V12 D11 W12 AH13 D8 AH14 AF7 AE24 AD23 AE6 AE23 AG14 AD5 AF4 AH3")), + Subsignal("ba", Pins( + "Y17 AB25")), + Subsignal("dqmh", Pins("AF13")), + Subsignal("dqml", Pins("AG13")), + Subsignal("cas_n", Pins("AA18")), + Subsignal("cs_n", Pins("Y18")), + Subsignal("ras_n", Pins("W14")), + Subsignal("we_n", Pins("AA19")), + IOStandard("3.3-V LVTTL"), Misc("SLEWRATE=FAST") + ), +] + # Platform ----------------------------------------------------------------------------------------- class Platform(AlteraPlatform): @@ -94,7 +112,8 @@ class Platform(AlteraPlatform): default_clk_period = 1e9/50e6 def __init__(self): - AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io) + # TODO uncancerify + AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io+_mister_sdram_module_io) def create_programmer(self): return USBBlaster() diff --git a/litex_boards/community/targets/de10nano.py b/litex_boards/community/targets/de10nano.py index f408984..bdae67b 100755 --- a/litex_boards/community/targets/de10nano.py +++ b/litex_boards/community/targets/de10nano.py @@ -11,8 +11,11 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex_boards.platforms import de10nano from litex.soc.integration.soc_core import * +from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * +from litedram.modules import AS4C16M16 +from litedram.phy import GENSDRPHY # CRG ---------------------------------------------------------------------------------------------- @@ -71,21 +74,52 @@ class BaseSoC(SoCCore): assert sys_clk_freq == int(50e6) platform = de10nano.Platform() - # SoCSDRAM --------------------------------------------------------------------------------- + # SoCCore --------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) + +# SDRAMSoC ------------------------------------------------------------------------------------------ + +class SDRAMSoC(SoCSDRAM): + def __init__(self, sys_clk_freq=int(50e6), **kwargs): + assert sys_clk_freq == int(50e6) + platform = de10nano.Platform() + + # SoCSDRAM --------------------------------------------------------------------------------- + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform) + + + # SDR SDRAM -------------------------------------------------------------------------------- + + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + sdram_module = AS4C16M16(self.clk_freq, "1:1") + self.register_sdram(self.sdrphy, + geom_settings = sdram_module.geom_settings, + timing_settings = sdram_module.timing_settings) + # Build -------------------------------------------------------------------------------------------- def main(): parser = argparse.ArgumentParser(description="LiteX SoC on DE10 Nano") + parser.add_argument("--with-sdram", action="store_true", + help="enable MiSTer SDRAM expansion board") builder_args(parser) - soc_core_args(parser) + #soc_core_args(parser) # TODO figure out how to get args for both + # core and sdram SoCs without breaking shit + soc_sdram_args(parser) args = parser.parse_args() + soc = None + if args.with_sdram: + soc = SDRAMSoC(**soc_sdram_argdict(args)) + else: + soc = BaseSoC(**soc_sdram_argdict(args)) - soc = BaseSoC(**soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build() From 1631b071c3bd212919ab76306dfb5b4da8651775 Mon Sep 17 00:00:00 2001 From: Paul Sajna Date: Thu, 30 Jan 2020 03:41:44 -0800 Subject: [PATCH 3/4] finish up sdram, passes memtest --- litex_boards/community/platforms/de10nano.py | 8 +++----- litex_boards/community/targets/de10nano.py | 5 +---- 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/litex_boards/community/platforms/de10nano.py b/litex_boards/community/platforms/de10nano.py index 162bae0..36c03ba 100644 --- a/litex_boards/community/platforms/de10nano.py +++ b/litex_boards/community/platforms/de10nano.py @@ -95,13 +95,11 @@ _mister_sdram_module_io = [ "E8 V12 D11 W12 AH13 D8 AH14 AF7 AE24 AD23 AE6 AE23 AG14 AD5 AF4 AH3")), Subsignal("ba", Pins( "Y17 AB25")), - Subsignal("dqmh", Pins("AF13")), - Subsignal("dqml", Pins("AG13")), Subsignal("cas_n", Pins("AA18")), Subsignal("cs_n", Pins("Y18")), Subsignal("ras_n", Pins("W14")), Subsignal("we_n", Pins("AA19")), - IOStandard("3.3-V LVTTL"), Misc("SLEWRATE=FAST") + IOStandard("3.3-V LVTTL") ), ] @@ -112,8 +110,8 @@ class Platform(AlteraPlatform): default_clk_period = 1e9/50e6 def __init__(self): - # TODO uncancerify - AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io+_mister_sdram_module_io) + AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io) + self.add_extension(_mister_sdram_module_io) def create_programmer(self): return USBBlaster() diff --git a/litex_boards/community/targets/de10nano.py b/litex_boards/community/targets/de10nano.py index bdae67b..d8148cd 100755 --- a/litex_boards/community/targets/de10nano.py +++ b/litex_boards/community/targets/de10nano.py @@ -66,6 +66,7 @@ class _CRG(Module): AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked) ] + self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) # BaseSoC ------------------------------------------------------------------------------------------ @@ -94,7 +95,6 @@ class SDRAMSoC(SoCSDRAM): # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) - # SDR SDRAM -------------------------------------------------------------------------------- self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) @@ -110,8 +110,6 @@ def main(): parser.add_argument("--with-sdram", action="store_true", help="enable MiSTer SDRAM expansion board") builder_args(parser) - #soc_core_args(parser) # TODO figure out how to get args for both - # core and sdram SoCs without breaking shit soc_sdram_args(parser) args = parser.parse_args() soc = None @@ -119,7 +117,6 @@ def main(): soc = SDRAMSoC(**soc_sdram_argdict(args)) else: soc = BaseSoC(**soc_sdram_argdict(args)) - builder = Builder(soc, **builder_argdict(args)) builder.build() From 36e1f1fe75bdba0416d2e74a5feb9dd41ec97ba6 Mon Sep 17 00:00:00 2001 From: Paul Sajna Date: Thu, 30 Jan 2020 05:01:46 -0800 Subject: [PATCH 4/4] rename sw to user_sw --- litex_boards/community/platforms/de10nano.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litex_boards/community/platforms/de10nano.py b/litex_boards/community/platforms/de10nano.py index 36c03ba..e4efa4d 100644 --- a/litex_boards/community/platforms/de10nano.py +++ b/litex_boards/community/platforms/de10nano.py @@ -22,10 +22,10 @@ _io = [ ("key", 0, Pins("AH17"), IOStandard("3.3-V LVTTL")), ("key", 1, Pins("AH16"), IOStandard("3.3-V LVTTL")), - ("sw", 0, Pins("Y24"), IOStandard("3.3-V LVTTL")), - ("sw", 1, Pins("W24"), IOStandard("3.3-V LVTTL")), - ("sw", 2, Pins("W21"), IOStandard("3.3-V LVTTL")), - ("sw", 3, Pins("W20"), IOStandard("3.3-V LVTTL")), + ("user_sw", 0, Pins("Y24"), IOStandard("3.3-V LVTTL")), + ("user_sw", 1, Pins("W24"), IOStandard("3.3-V LVTTL")), + ("user_sw", 2, Pins("W21"), IOStandard("3.3-V LVTTL")), + ("user_sw", 3, Pins("W20"), IOStandard("3.3-V LVTTL")), ("serial", 0, Subsignal("tx", Pins("AF13"), IOStandard("3.3-V LVTTL")), # Arduino_IO1