From 4fbf2fc7dee2378068371fcdf8d8a5ff5e67502c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 21 Apr 2022 15:32:19 +0200 Subject: [PATCH] targets: Replace self.add_wb_master with self.bus.add_master. --- litex_boards/targets/alinx_axu2cga.py | 2 +- litex_boards/targets/digilent_arty_z7.py | 2 +- litex_boards/targets/digilent_pynq_z1.py | 2 +- litex_boards/targets/digilent_zedboard.py | 2 +- litex_boards/targets/krtkl_snickerdoodle.py | 2 +- litex_boards/targets/redpitaya.py | 2 +- litex_boards/targets/siglent_sds1104xe.py | 2 +- litex_boards/targets/sqrl_fk33.py | 2 +- litex_boards/targets/xilinx_kv260.py | 2 +- litex_boards/targets/xilinx_zcu216.py | 2 +- litex_boards/targets/xilinx_zybo_z7.py | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/litex_boards/targets/alinx_axu2cga.py b/litex_boards/targets/alinx_axu2cga.py index a2114b1..e7f98a6 100755 --- a/litex_boards/targets/alinx_axu2cga.py +++ b/litex_boards/targets/alinx_axu2cga.py @@ -91,7 +91,7 @@ class BaseSoC(SoCCore): axi = self.cpu.add_axi_gp_master(2, 32), wishbone = wb_lpd, base_address = self.mem_map['csr']) - self.add_wb_master(wb_lpd) + self.bus.add_master(master=wb_lpd) self.bus.add_region("sram", SoCRegion( origin = self.cpu.mem_map["sram"], diff --git a/litex_boards/targets/digilent_arty_z7.py b/litex_boards/targets/digilent_arty_z7.py index 7438266..def214d 100755 --- a/litex_boards/targets/digilent_arty_z7.py +++ b/litex_boards/targets/digilent_arty_z7.py @@ -83,7 +83,7 @@ class BaseSoC(SoCCore): axi = self.cpu.add_axi_gp_master(), wishbone = wb_gp0, base_address = self.mem_map['csr']) - self.add_wb_master(wb_gp0) + self.bus.add_master(master=wb_gp0) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: diff --git a/litex_boards/targets/digilent_pynq_z1.py b/litex_boards/targets/digilent_pynq_z1.py index 0b7912b..7a5ee2f 100755 --- a/litex_boards/targets/digilent_pynq_z1.py +++ b/litex_boards/targets/digilent_pynq_z1.py @@ -81,7 +81,7 @@ class BaseSoC(SoCCore): axi = self.cpu.add_axi_gp_master(), wishbone = wb_gp0, base_address = 0x43c00000) - self.add_wb_master(wb_gp0) + self.bus.add_master(master=wb_gp0) # Video ------------------------------------------------------------------------------------ if with_video_terminal: diff --git a/litex_boards/targets/digilent_zedboard.py b/litex_boards/targets/digilent_zedboard.py index d9c631e..4024066 100755 --- a/litex_boards/targets/digilent_zedboard.py +++ b/litex_boards/targets/digilent_zedboard.py @@ -75,7 +75,7 @@ class BaseSoC(SoCCore): axi = self.cpu.add_axi_gp_master(), wishbone = wb_gp0, base_address = self.mem_map["csr"]) - self.add_wb_master(wb_gp0) + self.bus.add_master(master=wb_gp0) self.bus.add_region("sram", SoCRegion( origin=self.cpu.mem_map["sram"], diff --git a/litex_boards/targets/krtkl_snickerdoodle.py b/litex_boards/targets/krtkl_snickerdoodle.py index bb901a7..55bea1d 100755 --- a/litex_boards/targets/krtkl_snickerdoodle.py +++ b/litex_boards/targets/krtkl_snickerdoodle.py @@ -93,7 +93,7 @@ class BaseSoC(SoCCore): axi = self.cpu.add_axi_gp_master(), wishbone = wb_gp0, base_address = self.mem_map['csr']) - self.add_wb_master(wb_gp0) + self.bus.add_master(master=wb_gp0) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: diff --git a/litex_boards/targets/redpitaya.py b/litex_boards/targets/redpitaya.py index 98abc21..317539b 100755 --- a/litex_boards/targets/redpitaya.py +++ b/litex_boards/targets/redpitaya.py @@ -73,7 +73,7 @@ class BaseSoC(SoCCore): axi = self.cpu.add_axi_gp_master(), wishbone = wb_gp0, base_address = 0x43c00000) - self.add_wb_master(wb_gp0) + self.bus.add_master(master=wb_gp0) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: diff --git a/litex_boards/targets/siglent_sds1104xe.py b/litex_boards/targets/siglent_sds1104xe.py index 5ac5d88..be2ee0b 100755 --- a/litex_boards/targets/siglent_sds1104xe.py +++ b/litex_boards/targets/siglent_sds1104xe.py @@ -129,7 +129,7 @@ class BaseSoC(SoCCore): # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master") - self.add_wb_master(self.etherbone.wishbone.bus) + self.bus.add_master(master=self.etherbone.wishbone.bus) # Timing constraints eth_rx_clk = self.ethphy.crg.cd_eth_rx.clk diff --git a/litex_boards/targets/sqrl_fk33.py b/litex_boards/targets/sqrl_fk33.py index 45f251f..a4934eb 100755 --- a/litex_boards/targets/sqrl_fk33.py +++ b/litex_boards/targets/sqrl_fk33.py @@ -105,7 +105,7 @@ class BaseSoC(SoCCore): # Wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, base_address = self.mem_map["csr"]) - self.add_wb_master(self.pcie_bridge.wishbone) + self.bus.add_master(master=self.pcie_bridge.wishbone) # DMA0 self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, diff --git a/litex_boards/targets/xilinx_kv260.py b/litex_boards/targets/xilinx_kv260.py index a39f995..ceaf8d7 100755 --- a/litex_boards/targets/xilinx_kv260.py +++ b/litex_boards/targets/xilinx_kv260.py @@ -132,7 +132,7 @@ class BaseSoC(SoCCore): axi = self.cpu.add_axi_gp_master(), wishbone = wb_gp0, base_address = self.mem_map["csr"]) - self.add_wb_master(wb_gp0) + self.bus.add_master(master=wb_gp0) self.bus.add_region("sram", SoCRegion( origin=self.cpu.mem_map["sram"], size=2 * 1024 * 1024 * 1024) # DDR diff --git a/litex_boards/targets/xilinx_zcu216.py b/litex_boards/targets/xilinx_zcu216.py index c7bd2d0..670f4d2 100755 --- a/litex_boards/targets/xilinx_zcu216.py +++ b/litex_boards/targets/xilinx_zcu216.py @@ -112,7 +112,7 @@ class BaseSoC(SoCCore): axi = self.cpu.add_axi_gp_master(), wishbone = wb_gp0, base_address = self.mem_map["csr"]) - self.add_wb_master(wb_gp0) + self.bus.add_master(master=wb_gp0) self.bus.add_region("sram", SoCRegion( origin = self.cpu.mem_map["sram"], size = 2 * 1024 * 1024 * 1024) # DDR diff --git a/litex_boards/targets/xilinx_zybo_z7.py b/litex_boards/targets/xilinx_zybo_z7.py index 6ee1c39..1fcfd55 100755 --- a/litex_boards/targets/xilinx_zybo_z7.py +++ b/litex_boards/targets/xilinx_zybo_z7.py @@ -67,7 +67,7 @@ class BaseSoC(SoCCore): axi = self.cpu.add_axi_gp_master(), wishbone = wb_gp0, base_address = 0x43c00000) - self.add_wb_master(wb_gp0) + self.bus.add_master(master=wb_gp0) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: