From 5193f7155aeb15ce5edff4374e8563d4dbc062e0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 3 Dec 2019 09:37:18 +0100 Subject: [PATCH] partner/aller,nereid & tagus: fix compilation --- litex_boards/partner/targets/aller.py | 6 +++--- litex_boards/partner/targets/nereid.py | 4 ++-- litex_boards/partner/targets/tagus.py | 8 +++----- 3 files changed, 8 insertions(+), 10 deletions(-) diff --git a/litex_boards/partner/targets/aller.py b/litex_boards/partner/targets/aller.py index 69e1b55..8646a8b 100755 --- a/litex_boards/partner/targets/aller.py +++ b/litex_boards/partner/targets/aller.py @@ -50,7 +50,7 @@ class CRG(Module): # AllerSoC ----------------------------------------------------------------------------------------- class AllerSoC(SoCSDRAM): - SoCSDRAM.mem_map["csr"] = 0x00000000 + SoCSDRAM.mem_map["csr"] = 0x80000000 SoCSDRAM.mem_map["rom"] = 0x20000000 def __init__(self, platform, with_pcie_uart=True): @@ -88,7 +88,7 @@ class AllerSoC(SoCSDRAM): sdram_module = MT41J128M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + timing_settings = sdram_module.timing_settings) # PCIe ------------------------------------------------------------------------------------- # pcie phy @@ -103,7 +103,7 @@ class AllerSoC(SoCSDRAM): # pcie wishbone bridge self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, - lambda a: 1, shadow_base=self.shadow_base) + lambda a: 1, shadow_base=self.mem_map["csr"]) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma diff --git a/litex_boards/partner/targets/nereid.py b/litex_boards/partner/targets/nereid.py index 367ca0b..13c8b1a 100755 --- a/litex_boards/partner/targets/nereid.py +++ b/litex_boards/partner/targets/nereid.py @@ -50,7 +50,7 @@ class CRG(Module): # NereidSoC ---------------------------------------------------------------------------------------- class NereidSoC(SoCSDRAM): - SoCSDRAM.mem_map["csr"] = 0x00000000 + SoCSDRAM.mem_map["csr"] = 0x80000000 SoCSDRAM.mem_map["rom"] = 0x20000000 def __init__(self, platform, with_pcie_uart=True): @@ -103,7 +103,7 @@ class NereidSoC(SoCSDRAM): # pcie wishbone bridge self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, - lambda a: 1, shadow_base=self.shadow_base) + lambda a: 1, shadow_base=self.mem_map["csr"]) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma diff --git a/litex_boards/partner/targets/tagus.py b/litex_boards/partner/targets/tagus.py index c6f4e07..d34ac0a 100755 --- a/litex_boards/partner/targets/tagus.py +++ b/litex_boards/partner/targets/tagus.py @@ -52,7 +52,7 @@ class CRG(Module): # TagusSoC ----------------------------------------------------------------------------------------- class TagusSoC(SoCSDRAM): - SoCSDRAM.mem_map["csr"] = 0x00000000 + SoCSDRAM.mem_map["csr"] = 0x80000000 SoCSDRAM.mem_map["rom"] = 0x20000000 def __init__(self, platform, with_pcie_uart=True): @@ -97,9 +97,7 @@ class TagusSoC(SoCSDRAM): self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) self.pcie_phy.cd_pcie.clk.attr.add("keep") platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]") - platform.add_false_path_constraints( - self.crg.cd_sys.clk, - self.pcie_phy.cd_pcie.clk) + platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # pcie endpoint @@ -107,7 +105,7 @@ class TagusSoC(SoCSDRAM): # pcie wishbone bridge self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, - lambda a: 1, shadow_base=self.shadow_base) + lambda a: 1, shadow_base=self.mem_map["csr"]) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma