From 51c5d69586116cff9b673ecf0d45ab7b0e7d3eec Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 1 Feb 2021 13:20:32 +0100 Subject: [PATCH] targets/tec0117: use custom CPU/ROM/SRAM config to minimize resources. --- litex_boards/targets/tec0117.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/litex_boards/targets/tec0117.py b/litex_boards/targets/tec0117.py index b6c14fe..a22ec39 100755 --- a/litex_boards/targets/tec0117.py +++ b/litex_boards/targets/tec0117.py @@ -33,9 +33,11 @@ class BaseSoC(SoCCore): def __init__(self, bios_flash_offset, sys_clk_freq=int(12e6), with_sdram=False, sdram_rate="1:1", **kwargs): platform = tec0117.Platform() - # SoC can have littel a bram, as a treat - kwargs["integrated_sram_size"] = 2048*2 - kwargs["integrated_rom_size"] = 0 + # Use custom default configuration to fit in LittleBee. + kwargs["integrated_sram_size"] = 0x1000 + kwargs["integrated_rom_size"] = 0x6000 + kwargs["cpu_type"] = "vexriscv" + kwargs["cpu_variant"] = "lite" # Set CPU variant / reset address kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset @@ -173,7 +175,7 @@ def main(): sys_clk_freq = int(float(args.sys_clk_freq)), **soc_core_argdict(args) ) - builder = Builder(soc, **builder_argdict(args)) + builder = Builder(soc, **builder_argdict(args), bios_options=["TERM_MINI"]) builder.build(run=args.build) if args.load: