diff --git a/litex_boards/platforms/xcu1525.py b/litex_boards/platforms/xcu1525.py
new file mode 100644
index 0000000..4e16f4c
--- /dev/null
+++ b/litex_boards/platforms/xcu1525.py
@@ -0,0 +1,60 @@
+# This file is Copyright (c) 2020 David Shah <dave@ds0.me>
+# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
+# License: BSD
+
+from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
+from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
+
+# IOs ----------------------------------------------------------------------------------------------
+
+_io = [
+    # clk
+    ("clk300", 0,
+        Subsignal("n", Pins("AY38"), IOStandard("DIFF_SSTL12")),
+        Subsignal("p", Pins("AY37"), IOStandard("DIFF_SSTL12")),
+    ),
+
+    # led
+    ("user_led", 0, Pins("BC21"), IOStandard("LVCMOS12")),
+    ("user_led", 1, Pins("BB21"), IOStandard("LVCMOS12")),
+    ("user_led", 2, Pins("BA20"), IOStandard("LVCMOS12")),
+
+    # serial
+    ("serial", 0,
+        Subsignal("rx", Pins("BF18"), IOStandard("LVCMOS12")),
+        Subsignal("tx", Pins("BB20"), IOStandard("LVCMOS12")),
+    ),
+
+    # pcie
+    ("pcie_x4", 0,
+        Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")),
+        Subsignal("clk_n", Pins("AM10")),
+        Subsignal("clk_p", Pins("AM11")),
+        Subsignal("rx_n", Pins("AF1 AG3 AH1 AJ3")),
+        Subsignal("rx_p", Pins("AF2 AG4 AH2 AJ4")),
+        Subsignal("tx_n", Pins("AF6 AG8 AH6 AJ8")),
+        Subsignal("tx_p", Pins("AF7 AG9 AH7 AJ9")),
+    ),
+]
+
+_connectors = []
+
+# Platform -----------------------------------------------------------------------------------------
+
+class Platform(XilinxPlatform):
+    default_clk_name   = "clk300"
+    default_clk_period = 1e9/300e6
+
+    def __init__(self):
+        XilinxPlatform.__init__(self, "xcvu9p-fsgd2104-2l-e", _io, _connectors, toolchain="vivado")
+
+    def create_programmer(self):
+        return VivadoProgrammer()
+
+    def do_finalize(self, fragment):
+        XilinxPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk300", 0, loose=True), 1e9/300e6)
+        # For passively cooled boards, overheating is a significant risk if airflow isn't sufficient
+        self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]")
+        # Reduce programming time
+        self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]")
diff --git a/litex_boards/targets/xcu1525.py b/litex_boards/targets/xcu1525.py
new file mode 100755
index 0000000..73502bd
--- /dev/null
+++ b/litex_boards/targets/xcu1525.py
@@ -0,0 +1,71 @@
+#!/usr/bin/env python3
+
+# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
+# License: BSD
+
+import os
+import argparse
+
+from migen import *
+
+from litex_boards.platforms import xcu1525
+
+from litex.soc.cores.clock import *
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.soc_sdram import *
+from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
+
+# CRG ----------------------------------------------------------------------------------------------
+
+class _CRG(Module):
+    def __init__(self, platform, sys_clk_freq):
+        self.clock_domains.cd_sys    = ClockDomain()
+
+        # # #
+
+        self.submodules.pll = pll = USPMMCM(speedgrade=-2)
+        pll.register_clkin(platform.request("clk300"), 300e6)
+        pll.create_clkout(self.cd_sys, sys_clk_freq)
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+class BaseSoC(SoCCore):
+    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
+        platform = xcu1525.Platform()
+
+        # SoCCore ----------------------------------------------------------------------------------
+        SoCCore.__init__(self, platform, sys_clk_freq,
+            ident          = "LiteX SoC on XCU1525",
+            ident_version  = True,
+            **kwargs)
+
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = _CRG(platform, sys_clk_freq)
+
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = platform.request_all("user_led"),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
+# Build --------------------------------------------------------------------------------------------
+
+def main():
+    parser = argparse.ArgumentParser(description="LiteX SoC on XCU1525")
+    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    builder_args(parser)
+    soc_sdram_args(parser)
+    args = parser.parse_args()
+
+    soc = BaseSoC(**soc_sdram_argdict(args))
+    builder = Builder(soc, **builder_argdict(args))
+    builder.build(run=args.build)
+
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
+
+if __name__ == "__main__":
+    main()