From 52c9648176c7e04d6375536b5ecc9e04db259b96 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 Apr 2020 15:20:36 +0200 Subject: [PATCH] arty_s7: fix copyrights, rename to arty_s7, various minor changes to make it similar to others targets. --- .../platforms/{artys7.py => arty_s7.py} | 76 ++++++++++--------- .../targets/{artys7.py => arty_s7.py} | 19 +++-- test/test_targets.py | 3 + 3 files changed, 51 insertions(+), 47 deletions(-) rename litex_boards/platforms/{artys7.py => arty_s7.py} (81%) rename litex_boards/targets/{artys7.py => arty_s7.py} (86%) diff --git a/litex_boards/platforms/artys7.py b/litex_boards/platforms/arty_s7.py similarity index 81% rename from litex_boards/platforms/artys7.py rename to litex_boards/platforms/arty_s7.py index ecf7b22..2fe63d3 100644 --- a/litex_boards/platforms/artys7.py +++ b/litex_boards/platforms/arty_s7.py @@ -1,5 +1,5 @@ -# This file is Copyright (c) 2015 Yann Sionneau -# This file is Copyright (c) 2015-2019 Florent Kermarrec +# This file is Copyright (c) 2018 William D. Jones +# This file is Copyright (c) 2020 Staf Verhaegen # License: BSD from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc @@ -30,7 +30,7 @@ _io = [ ("user_sw", 0, Pins("H14"), IOStandard("LVCMOS33")), ("user_sw", 1, Pins("H18"), IOStandard("LVCMOS33")), ("user_sw", 2, Pins("G18"), IOStandard("LVCMOS33")), - ("user_sw", 3, Pins("M5"), IOStandard("SSTL135")), + ("user_sw", 3, Pins("M5"), IOStandard("SSTL135")), ("user_btn", 0, Pins("G15"), IOStandard("LVCMOS33")), ("user_btn", 1, Pins("K16"), IOStandard("LVCMOS33")), @@ -47,7 +47,7 @@ _io = [ IOStandard("LVCMOS33")), ("spi", 0, - Subsignal("clk", Pins("G16")), + Subsignal("clk", Pins("G16")), Subsignal("cs_n", Pins("H16")), Subsignal("mosi", Pins("H17")), Subsignal("miso", Pins("K14")), @@ -62,16 +62,16 @@ _io = [ ("spiflash4x", 0, # clock needs to be accessed through STARTUPE2 Subsignal("cs_n", Pins("M13")), - Subsignal("clk", Pins("D11")), - Subsignal("dq", Pins("K17", "K18", "L14", "M15")), + Subsignal("clk", Pins("D11")), + Subsignal("dq", Pins("K17", "K18", "L14", "M15")), IOStandard("LVCMOS33") ), ("spiflash", 0, # clock needs to be accessed through STARTUPE2 Subsignal("cs_n", Pins("M13")), - Subsignal("clk", Pins("D11")), + Subsignal("clk", Pins("D11")), Subsignal("mosi", Pins("K17")), Subsignal("miso", Pins("K18")), - Subsignal("wp", Pins("L14")), + Subsignal("wp", Pins("L14")), Subsignal("hold", Pins("M15")), IOStandard("LVCMOS33") ), @@ -84,8 +84,8 @@ _io = [ Subsignal("ba", Pins("V5 T1 U3"), IOStandard("SSTL135")), Subsignal("ras_n", Pins("U1"), IOStandard("SSTL135")), Subsignal("cas_n", Pins("V3"), IOStandard("SSTL135")), - Subsignal("we_n", Pins("P7"), IOStandard("SSTL135")), - Subsignal("cs_n", Pins("R3"), IOStandard("SSTL135")), + Subsignal("we_n", Pins("P7"), IOStandard("SSTL135")), + Subsignal("cs_n", Pins("R3"), IOStandard("SSTL135")), Subsignal("dm", Pins("K4 M3"), IOStandard("SSTL135")), Subsignal("dq", Pins( "K2 K3 L4 M6 K6 M4 L5 L6", @@ -100,8 +100,8 @@ _io = [ Misc("IN_TERM=UNTUNED_SPLIT_40")), Subsignal("clk_p", Pins("R5"), IOStandard("DIFF_SSTL135")), Subsignal("clk_n", Pins("T4"), IOStandard("DIFF_SSTL135")), - Subsignal("cke", Pins("T2"), IOStandard("SSTL135")), - Subsignal("odt", Pins("P5"), IOStandard("SSTL135")), + Subsignal("cke", Pins("T2"), IOStandard("SSTL135")), + Subsignal("odt", Pins("P5"), IOStandard("SSTL135")), Subsignal("reset_n", Pins("J6"), IOStandard("SSTL135")), Misc("SLEW=FAST"), ), @@ -116,16 +116,16 @@ _connectors = [ ("pmodd", "V15 U12 V13 T12 T13 R11 T11 U11"), ("ck_io", { # Outer Digital Header - "ck_io0" : "L13", - "ck_io1" : "N13", - "ck_io2" : "L16", - "ck_io3" : "R14", - "ck_io4" : "T14", - "ck_io5" : "R16", - "ck_io6" : "R17", - "ck_io7" : "V17", - "ck_io8" : "R15", - "ck_io9" : "T15", + "ck_io0" : "L13", + "ck_io1" : "N13", + "ck_io2" : "L16", + "ck_io3" : "R14", + "ck_io4" : "T14", + "ck_io5" : "R16", + "ck_io6" : "R17", + "ck_io7" : "V17", + "ck_io8" : "R15", + "ck_io9" : "T15", "ck_io10" : "H16", "ck_io11" : "H17", "ck_io12" : "K14", @@ -158,23 +158,24 @@ _connectors = [ "ck_a5" : "D18", # Inner Analog Header as Digital IO - "ck_a6" : "B14", - "ck_a7" : "A14", - "ck_a8" : "D16", - "ck_a9" : "D17", + "ck_a6" : "B14", + "ck_a7" : "A14", + "ck_a8" : "D16", + "ck_a9" : "D17", "ck_a10" : "D14", "ck_a11" : "D15", - } ), + } + ), ("XADC", { # Outer Analog Header - "vaux0_p" : "B13", - "vaux0_n" : "A13", - "vaux1_p" : "B15", - "vaux1_n" : "A15", - "vaux9_p" : "E12", - "vaux9_n" : "D12", - "vaux2_p" : "B17", - "vaux2_n" : "A17", + "vaux0_p" : "B13", + "vaux0_n" : "A13", + "vaux1_p" : "B15", + "vaux1_n" : "A15", + "vaux9_p" : "E12", + "vaux9_n" : "D12", + "vaux2_p" : "B17", + "vaux2_n" : "A17", "vaux10_p" : "C17", "vaux10_n" : "B18", "vaux11_p" : "E16", @@ -185,13 +186,14 @@ _connectors = [ "vaux8_n" : "A14", "vaux3_p" : "D16", "vaux3_n" : "D17", - } ), + } + ), ] # Platform ----------------------------------------------------------------------------------------- class Platform(XilinxPlatform): - default_clk_name = "clk100" + default_clk_name = "clk100" default_clk_period = 1e9/100e6 def __init__(self, variant="s7-50"): diff --git a/litex_boards/targets/artys7.py b/litex_boards/targets/arty_s7.py similarity index 86% rename from litex_boards/targets/artys7.py rename to litex_boards/targets/arty_s7.py index 00a09a5..b816d1d 100755 --- a/litex_boards/targets/artys7.py +++ b/litex_boards/targets/arty_s7.py @@ -1,20 +1,20 @@ #!/usr/bin/env python3 # This file is Copyright (c) 2015-2019 Florent Kermarrec , -# Copyright (c) 2020 Staf Verhaegen +# This file is Copyright (c) 2020 Staf Verhaegen # License: BSD import argparse -from migen import Module, ClockDomain +from migen import * -from ..platforms import artys7 +from litex_boards.platforms import arty_s7 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict -from litex.soc.cores.clock import S7PLL, S7IDELAYCTRL -from litex.soc.integration.soc_core import SoCCore -from litex.soc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict -from litex.soc.integration.builder import Builder, builder_args, builder_argdict +from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * +from litex.soc.integration.soc_sdram import * +from litex.soc.integration.builder import * from litedram.modules import MT41K128M16 from litedram.phy import s7ddrphy @@ -46,7 +46,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), **kwargs): - platform = artys7.Platform() + platform = arty_s7.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) @@ -81,8 +81,7 @@ def main(): vivado_build_args(parser) args = parser.parse_args() - soc = BaseSoC(with_ethernet=False, with_etherbone=False, - **soc_sdram_argdict(args)) + soc = BaseSoC(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build(**vivado_build_argdict(args)) diff --git a/test/test_targets.py b/test/test_targets.py index adccc79..4a450d3 100644 --- a/test/test_targets.py +++ b/test/test_targets.py @@ -36,6 +36,9 @@ class TestTargets(unittest.TestCase): platforms.append("pipistrello") platforms.append("sp605") + # Xilinx Spartan7 + platforms.append("arty_s7") + # Xilinx Artix7 platforms.append("ac701") platforms.append("aller")