From 7442c2dada5fd72806d0d3d313a07cfcaa177752 Mon Sep 17 00:00:00 2001 From: Michael Betz Date: Mon, 8 Feb 2021 19:04:01 -0800 Subject: [PATCH] vc707.py: clk156 add missing constraint --- litex_boards/platforms/vc707.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex_boards/platforms/vc707.py b/litex_boards/platforms/vc707.py index 3cb4340..d4acf02 100644 --- a/litex_boards/platforms/vc707.py +++ b/litex_boards/platforms/vc707.py @@ -642,4 +642,5 @@ class Platform(XilinxPlatform): def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6) + self.add_period_constraint(self.lookup_request("clk156", loose=True), 1e9/156e6) self.add_period_constraint(self.lookup_request("sgmii_clock", loose=True), 1e9/125e6)