From 533d25e845227e6fe3f4a3c550d5b2d97f127d86 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 27 Jul 2021 17:38:25 +0200 Subject: [PATCH] 1bitsquared_icebreaker: Enable LiteSPI Master but reduce FIFO depth to reduce resource usage. Already better regarding resource usage: Info: ICESTORM_LC: 2938/ 5280 55% Info: ICESTORM_RAM: 2/ 30 6% Info: SB_IO: 15/ 96 15% Info: SB_GB: 8/ 8 100% Info: ICESTORM_PLL: 1/ 1 100% Info: SB_WARMBOOT: 0/ 1 0% Info: ICESTORM_DSP: 0/ 8 0% Info: ICESTORM_HFOSC: 0/ 1 0% Info: ICESTORM_LFOSC: 0/ 1 0% Info: SB_I2C: 0/ 2 0% Info: SB_SPI: 0/ 2 0% Info: IO_I3C: 0/ 2 0% Info: SB_LEDDA_IP: 0/ 1 0% Info: SB_RGBA_DRV: 0/ 1 0% Info: ICESTORM_SPRAM: 4/ 4 100% --- litex_boards/targets/1bitsquared_icebreaker.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/targets/1bitsquared_icebreaker.py b/litex_boards/targets/1bitsquared_icebreaker.py index 606903a..124058b 100755 --- a/litex_boards/targets/1bitsquared_icebreaker.py +++ b/litex_boards/targets/1bitsquared_icebreaker.py @@ -104,7 +104,7 @@ class BaseSoC(SoCCore): from litespi.phy.generic import LiteSPIPHY from litespi import LiteSPI self.submodules.spiflash_phy = LiteSPIPHY(platform.request("spiflash4x"), W25Q128JV(Codes.READ_1_1_4)) - self.submodules.spiflash_mmap = LiteSPI(self.spiflash_phy, clk_freq=sys_clk_freq, with_master=False, mmap_endianness=self.cpu.endianness) + self.submodules.spiflash_mmap = LiteSPI(self.spiflash_phy, clk_freq=sys_clk_freq, master_fifo_depth=1, mmap_endianness=self.cpu.endianness) spiflash_region = SoCRegion(origin=self.mem_map.get("spiflash", None), size=W25Q128JV.total_size, cached=False) self.bus.add_slave(name="spiflash", slave=self.spiflash_mmap.bus, region=spiflash_region) else: