From 5359fc5bfcd2a623f05bc0b7bdb4037b620853c5 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Mon, 17 Jan 2022 12:47:39 +0100 Subject: [PATCH] antmicro_datacenter: use A7DDRPHY Signed-off-by: Karol Gugala --- .../antmicro_datacenter_ddr4_test_board.py | 22 ++++++++++--------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py index 70ab772..d799516 100755 --- a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py +++ b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py @@ -21,7 +21,7 @@ from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser from litedram.modules import MTA18ASF2G72PZ -from litedram.phy.s7ddrphy import K7DDRPHY +from litedram.phy.s7ddrphy import A7DDRPHY from liteeth.phy import LiteEthS7PHYRGMII from litex.soc.cores.hyperbus import HyperRAM @@ -30,19 +30,21 @@ from litex.soc.cores.hyperbus import HyperRAM class _CRG(Module): def __init__(self, platform, sys_clk_freq, iodelay_clk_freq): - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) - self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) - self.clock_domains.cd_idelay = ClockDomain() + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) + self.clock_domains.cd_idelay = ClockDomain() # # # self.submodules.pll = pll = S7PLL(speedgrade=-1) pll.register_clkin(platform.request("clk100"), 100e6) - pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq) - pll.create_clkout(self.cd_sys4x, 4 * sys_clk_freq) - pll.create_clkout(self.cd_idelay, iodelay_clk_freq) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4 * sys_clk_freq) + pll.create_clkout(self.cd_sys4x_dqs, 4 * sys_clk_freq, phase=90) + pll.create_clkout(self.cd_idelay, iodelay_clk_freq) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) @@ -65,7 +67,7 @@ class BaseSoC(SoCCore): # DDR4 SDRAM RDIMM ------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.ddrphy = K7DDRPHY(platform.request("ddr4"), + self.submodules.ddrphy = A7DDRPHY(platform.request("ddr4"), memtype = "DDR4", iodelay_clk_freq = iodelay_clk_freq, sys_clk_freq = sys_clk_freq,