From 537f494cbbb4c21895b5e95e09387f4fe304276c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 25 Jan 2021 09:14:46 +0100 Subject: [PATCH] arrow_sockit: review/harmonize with others boards. --- litex_boards/platforms/arrow_sockit.py | 70 +++++++++++++------------- litex_boards/targets/arrow_sockit.py | 16 ++---- 2 files changed, 41 insertions(+), 45 deletions(-) diff --git a/litex_boards/platforms/arrow_sockit.py b/litex_boards/platforms/arrow_sockit.py index e90e6a1..7b0303a 100644 --- a/litex_boards/platforms/arrow_sockit.py +++ b/litex_boards/platforms/arrow_sockit.py @@ -1,9 +1,7 @@ # # This file is part of LiteX-Boards. # -# I (HB) used the similar de1soc board as a starting point, therefore: -# Copyright (c) 2019 Antony Pavlov -# SocKit adaption (c) 2020 Hans Baier +# Copyright (c) 2020 Hans Baier # # SPDX-License-Identifier: BSD-2-Clause @@ -21,17 +19,17 @@ _io = [ ("user_led", 0, Pins("AF10"), IOStandard("3.3-V LVTTL")), ("user_led", 1, Pins("AD10"), IOStandard("3.3-V LVTTL")), ("user_led", 2, Pins("AE11"), IOStandard("3.3-V LVTTL")), - ("user_led", 3, Pins("AD7"), IOStandard("3.3-V LVTTL")), + ("user_led", 3, Pins("AD7"), IOStandard("3.3-V LVTTL")), # Buttons - ("user_btn", 0, Pins("AE9"), IOStandard("3.3-V LVTTL")), + ("user_btn", 0, Pins("AE9"), IOStandard("3.3-V LVTTL")), ("user_btn", 1, Pins("AE12"), IOStandard("3.3-V LVTTL")), - ("user_btn", 2, Pins("AD9"), IOStandard("3.3-V LVTTL")), + ("user_btn", 2, Pins("AD9"), IOStandard("3.3-V LVTTL")), ("user_btn", 3, Pins("AD11"), IOStandard("3.3-V LVTTL")), # Switches - ("user_sw", 0, Pins("W25"), IOStandard("3.3-V LVTTL")), - ("user_sw", 1, Pins("V25"), IOStandard("3.3-V LVTTL")), + ("user_sw", 0, Pins("W25"), IOStandard("3.3-V LVTTL")), + ("user_sw", 1, Pins("V25"), IOStandard("3.3-V LVTTL")), ("user_sw", 2, Pins("AC28"), IOStandard("3.3-V LVTTL")), ("user_sw", 3, Pins("AC29"), IOStandard("3.3-V LVTTL")), @@ -41,50 +39,50 @@ _io = [ "AJ14 AK14 AH12 AJ12 AG15 AH15 AK12 AK13", "AH13 AH14 AJ9 AK9 AK7 AK8 AG12"), IOStandard("SSTL15"), - Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT") ), - Subsignal("ba", Pins("AH10 AJ11 AK11"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), - Subsignal("ras_n", Pins("AH8"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), - Subsignal("cas_n", Pins("AH7"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), - Subsignal("we_n", Pins("AJ6"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), + Subsignal("ba", Pins("AH10 AJ11 AK11"), IOStandard("SSTL-15 CLASS I"), ), + Subsignal("ras_n", Pins("AH8"), IOStandard("SSTL-15 CLASS I")), + Subsignal("cas_n", Pins("AH7"), IOStandard("SSTL-15 CLASS I")), + Subsignal("we_n", Pins("AJ6"), IOStandard("SSTL-15 CLASS I")), Subsignal("dm", Pins("AH17 AG23 AK23 AJ27"), IOStandard("SSTL-15 CLASS I"), Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION") ), Subsignal("dq", Pins( - "AF18 AE17 AG16 AF16 AH20 AG21 AJ16 AH18", - "AK18 AJ17 AG18 AK19 AG20 AF19 AJ20 AH24", - "AE19 AE18 AG22 AK22 AF21 AF20 AH23 AK24", - "AF24 AF23 AJ24 AK26 AE23 AE22 AG25 AK27"), - IOStandard("SSTL-15 CLASS I"), - Misc("INPUT_TERMINATION=PARALLEL 50 OHM WITH CALIBRATION"), - Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION"), + "AF18 AE17 AG16 AF16 AH20 AG21 AJ16 AH18", + "AK18 AJ17 AG18 AK19 AG20 AF19 AJ20 AH24", + "AE19 AE18 AG22 AK22 AF21 AF20 AH23 AK24", + "AF24 AF23 AJ24 AK26 AE23 AE22 AG25 AK27"), + IOStandard("SSTL-15 CLASS I"), + Misc("INPUT_TERMINATION=PARALLEL 50 OHM WITH CALIBRATION"), + Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION"), ), - Subsignal("dqs_p", Pins("V16 V17 Y17 AC20"), + Subsignal("dqs_p", Pins("V16 V17 Y17 AC20"), IOStandard("DIFFERENTIAL 1.5-V SSTL CLASS I"), Misc("INPUT_TERMINATION=PARALLEL 50 OHM WITH CALIBRATION"), Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION") ), - Subsignal("dqs_n", Pins("W16 W17 AA18 AD19"), + Subsignal("dqs_n", Pins("W16 W17 AA18 AD19"), IOStandard("DIFFERENTIAL 1.5-V SSTL CLASS I"), Misc("INPUT_TERMINATION=PARALLEL 50 OHM WITH CALIBRATION"), Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION") ), - Subsignal("clk_p", Pins("AA14"), + Subsignal("clk_p", Pins("AA14"), IOStandard("DIFFERENTIAL 1.5-V SSTL CLASS I"), Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION"), Misc("D5_DELAY=2") ), - Subsignal("clk_n", Pins("AA15"), + Subsignal("clk_n", Pins("AA15"), IOStandard("DIFFERENTIAL 1.5-V SSTL CLASS I"), Misc("OUTPUT_TERMINATION=SERIES 50 OHM WITH CALIBRATION"), Misc("D5_DELAY=2") ), - Subsignal("cs_n", Pins("AB15"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), - Subsignal("cke", Pins("AJ21"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), - Subsignal("odt", Pins("AE16"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), - Subsignal("reset_n", Pins("AK21"), IOStandard("SSTL-15 CLASS I"), Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")), - Subsignal("rzq", Pins("AG1"), IOStandard("SSTL-15")), + Subsignal("cs_n", Pins("AB15"), IOStandard("SSTL-15 CLASS I")), + Subsignal("cke", Pins("AJ21"), IOStandard("SSTL-15 CLASS I")), + Subsignal("odt", Pins("AE16"), IOStandard("SSTL-15 CLASS I")), + Subsignal("reset_n", Pins("AK21"), IOStandard("SSTL-15 CLASS I")), + Subsignal("rzq", Pins("AG1"), IOStandard("SSTL-15")), + Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT") ), # VGA @@ -99,11 +97,13 @@ _io = [ IOStandard("3.3-V LVTTL") ), + # IrDA ("irda", 0, Subsignal("irda_rxd", Pins("AH2")), IOStandard("3.3-V LVTTL") ), + # Temperatue ("temperature", 0, Subsignal("temp_cs_n", Pins("AF8")), Subsignal("temp_din", Pins("AG7")), @@ -112,6 +112,7 @@ _io = [ IOStandard("3.3-V LVTTL") ), + # Audio ("audio", 0, Subsignal("aud_adclrck", Pins("AG30")), Subsignal("aud_adcdat", Pins("AC27")), @@ -126,6 +127,8 @@ _io = [ ) ] +# Connectors --------------------------------------------------------------------------------------- + _connectors_hsmc_gpio_daughterboard = [ ("J2", "G15 F14 H15 F15 A13 G13 B13 H14 B11 E13 - - " + "C12 F13 B8 B12 C8 C13 A10 D10 A11 D11 B7 D12 C7 E12 A5 D9 - - " + @@ -146,19 +149,18 @@ _connectors_hsmc_gpio_daughterboard = [ # Platform ----------------------------------------------------------------------------------------- _device_map = { - "revB/C": "5CSXFC6D6F31C8ES", - "revD": "5CSXFC6D6F31C8", + "revb" : "5CSXFC6D6F31C8ES", + "revc" : "5CSXFC6D6F31C8ES", + "revd" : "5CSXFC6D6F31C8", } class Platform(AlteraPlatform): default_clk_name = "clk50" default_clk_period = 1e9/50e6 - def __init__(self, revision="revB/C"): + def __init__(self, revision="revd"): assert revision in _device_map.keys() self.revision = revision - - # Yes, the HSMC GPIO board is optional, but only it has generic connectors AlteraPlatform.__init__(self, _device_map[revision], _io, connectors=_connectors_hsmc_gpio_daughterboard) def create_programmer(self): diff --git a/litex_boards/targets/arrow_sockit.py b/litex_boards/targets/arrow_sockit.py index 030e8d1..34cf133 100755 --- a/litex_boards/targets/arrow_sockit.py +++ b/litex_boards/targets/arrow_sockit.py @@ -2,10 +2,7 @@ # # This file is part of LiteX-Boards. # -# I (HB) used the similar de1soc board as a starting point, therefore: -# Copyright (c) 2019 Antony Pavlov -# SocKit adaption (c) 2020 Hans Baier -# +# Copyright (c) 2020 Hans Baier # SPDX-License-Identifier: BSD-2-Clause import os @@ -15,7 +12,6 @@ from migen.fhdl.module import Module from migen.fhdl.structure import Signal, ClockDomain from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.build.io import DDROutput from litex.soc.cores.clock import CycloneVPLL from litex.soc.integration.builder import Builder, builder_args, builder_argdict from litex.soc.integration.soc_core import SoCCore @@ -45,12 +41,10 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(50e6), revisionD=False, **kwargs): - revision = "revD" if revisionD else "revB/C" + def __init__(self, sys_clk_freq=int(50e6), revision="revd", **kwargs): platform = arrow_sockit.Platform(revision) - # Defaults to Crossover UART, because Serial is attached to the HPS - # and thus not available to the FPGA + # Defaults to Crossover UART because serial is attached to the HPS and cannot be used. if kwargs["uart_name"] == "serial": kwargs["uart_name"] = "crossover" @@ -76,7 +70,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on SoCKit") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--revisionD", action="store_true", help="board revision D, otherwise the more widespread revision B/C is assumed") + parser.add_argument("--revision", default="revd", help="Board revision: revb (default), revc or revd") parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") builder_args(parser) soc_sdram_args(parser) @@ -84,7 +78,7 @@ def main(): soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), - revisionD = args.revisionD, + revision = args.revision, **soc_sdram_argdict(args) ) builder = Builder(soc, **builder_argdict(args))