From 538878ce13ba1f5cdc41bf50edf3ae1da16af6fc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 1 Feb 2021 13:18:16 +0100 Subject: [PATCH] =?UTF-8?q?tec0117:=20disable=20BIOS=20XIP=20from=20SPI=20?= =?UTF-8?q?Flash=20for=20now=20since=20not=20working=20(SP=C3=8F=20Flash?= =?UTF-8?q?=20set=20to=20power=20down=20mode=20with=20bitstream=3F).?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- litex_boards/targets/tec0117.py | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/litex_boards/targets/tec0117.py b/litex_boards/targets/tec0117.py index 1f902ae..b6c14fe 100755 --- a/litex_boards/targets/tec0117.py +++ b/litex_boards/targets/tec0117.py @@ -53,11 +53,12 @@ class BaseSoC(SoCCore): self.add_spi_flash(mode="1x", dummy_cycles=8) # Add ROM linker region -------------------------------------------------------------------- - self.bus.add_region("rom", SoCRegion( - origin = self.mem_map["spiflash"] + bios_flash_offset, - size = 8*mB, - linker = True) - ) + # FIXME: SPI Flash does not seem responding, power down set after loading bitstream? + #self.bus.add_region("rom", SoCRegion( + # origin = self.mem_map["spiflash"] + bios_flash_offset, + # size = 32*kB, + # linker = True) + #) # SDR SDRAM (WIP) -------------------------------------------------------------------------- if with_sdram: