From 53b6bf035a9f0d5403399247cb53c5a6d4e314f0 Mon Sep 17 00:00:00 2001 From: mkuhn99 Date: Thu, 24 Nov 2022 16:03:12 +0100 Subject: [PATCH] fixed parser --- litex_boards/targets/xilinx_zybo_z7.py | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/litex_boards/targets/xilinx_zybo_z7.py b/litex_boards/targets/xilinx_zybo_z7.py index b38b1b3..f3d1611 100755 --- a/litex_boards/targets/xilinx_zybo_z7.py +++ b/litex_boards/targets/xilinx_zybo_z7.py @@ -170,15 +170,10 @@ class BaseSoC(SoCCore): def main(): from litex.build.parser import LiteXArgumentParser - parser = LiteXArgumentParser(description="LiteX SoC on Zybo Z7") - target_group = parser.add_argument_group(title="Target options") - target_group.add_argument("--build", action="store_true", help="Build design.") - target_group.add_argument("--load", action="store_true", help="Load bitstream.") - target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") - target_group.add_argument("--variant", default="z7-10", help="Board variant (z7-10 or z7-20).") - target_group.add_argument("--with-ps7", action="store_true", help="Add the PS7 as slave for soft CPUs.") - builder_args(parser) - soc_core_args(parser) + parser = LiteXArgumentParser(platform=digilent_zybo_z7.Platform, description="LiteX SoC on Zybo Z7") + parser.add_target_argument("--sys-clk-freq", default=125e6, type=float, help="System clock frequency.") + parser.add_target_argument("--variant", default="z7-10", help="Board variant (z7-10 or z7-20).") + parser.add_target_argument("--with-ps7", action="store_true", help="Add the PS7 as slave for soft CPUs.") args = parser.parse_args() soc = BaseSoC(