diff --git a/litex_boards/__init__.py b/litex_boards/__init__.py index 507861f..35d7f7d 100644 --- a/litex_boards/__init__.py +++ b/litex_boards/__init__.py @@ -29,6 +29,7 @@ vendors = [ "sqrl", "terasic", "trenz", + "tul", "xilinx", ] diff --git a/litex_boards/platforms/tul_pynq_z2.py b/litex_boards/platforms/tul_pynq_z2.py new file mode 100644 index 0000000..e0c9959 --- /dev/null +++ b/litex_boards/platforms/tul_pynq_z2.py @@ -0,0 +1,100 @@ +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2019-2020 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +from litex.build.generic_platform import * +from litex.build.xilinx import XilinxPlatform, VivadoProgrammer + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + # Clk / Rst + ("clk125", 0, Pins("H16"), IOStandard("LVCMOS33")), + + # Leds + ("user_led", 0, Pins("R14"), IOStandard("LVCMOS33")), + ("user_led", 1, Pins("P14"), IOStandard("LVCMOS33")), + ("user_led", 2, Pins("N16"), IOStandard("LVCMOS33")), + ("user_led", 3, Pins("M14"), IOStandard("LVCMOS33")), + + # Switches + ("user_sw", 0, Pins("M20"), IOStandard("LVCMOS33")), + ("user_sw", 1, Pins("M19"), IOStandard("LVCMOS33")), + + # Buttons + ("user_btn", 0, Pins("D19"), IOStandard("LVCMOS33")), + ("user_btn", 1, Pins("D20"), IOStandard("LVCMOS33")), + ("user_btn", 2, Pins("L20"), IOStandard("LVCMOS33")), + ("user_btn", 3, Pins("L19"), IOStandard("LVCMOS33")), + + # Serial + ("serial", 0, + Subsignal("tx", Pins("T14")), #AR0 + Subsignal("rx", Pins("U12")), #AR1 + IOStandard("LVCMOS33") + ), +] + +_ps7_io = [ + # PS7 + ("ps7_clk", 0, Pins(1)), + ("ps7_porb", 0, Pins(1)), + ("ps7_srstb", 0, Pins(1)), + ("ps7_mio", 0, Pins(54)), + ("ps7_ddram", 0, + Subsignal("addr", Pins(15)), + Subsignal("ba", Pins(3)), + Subsignal("cas_n", Pins(1)), + Subsignal("ck_n", Pins(1)), + Subsignal("ck_p", Pins(1)), + Subsignal("cke", Pins(1)), + Subsignal("cs_n", Pins(1)), + Subsignal("dm", Pins(4)), + Subsignal("dq", Pins(32)), + Subsignal("dqs_n", Pins(4)), + Subsignal("dqs_p", Pins(4)), + Subsignal("odt", Pins(1)), + Subsignal("ras_n", Pins(1)), + Subsignal("reset_n", Pins(1)), + Subsignal("we_n", Pins(1)), + Subsignal("vrn", Pins(1)), + Subsignal("vrp", Pins(1)), + ), +] + +_usb_uart_pmod_io = [ + # USB-UART PMOD on JB: + # - https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/ + ("usb_uart", 0, + Subsignal("tx", Pins("pmodb:1")), + Subsignal("rx", Pins("pmodb:2")), + IOStandard("LVCMOS33") + ), +] + +# Connectors --------------------------------------------------------------------------------------- + +_connectors = [ + ("pmoda", "Y18 Y19 Y16 Y17 U18 U19 W18 W19"), + ("pmodb", "W14 Y14 T11 T10 V16 W16 V12 W13"), +] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(XilinxPlatform): + default_clk_name = "clk125" + default_clk_period = 1e9/125e6 + + def __init__(self): + XilinxPlatform.__init__(self, "xc7z020clg400-1", _io, _connectors, toolchain="vivado") + self.add_extension(_ps7_io) + self.add_extension(_usb_uart_pmod_io) + + def create_programmer(self): + return VivadoProgrammer() + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6) diff --git a/litex_boards/targets/tul_pynq_z2.py b/litex_boards/targets/tul_pynq_z2.py new file mode 100755 index 0000000..e383028 --- /dev/null +++ b/litex_boards/targets/tul_pynq_z2.py @@ -0,0 +1,107 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2019-2020 Florent Kermarrec , +# SPDX-License-Identifier: BSD-2-Clause + +import os +import argparse + +from migen import * + +from litex_boards.platforms import pynq_z2 +from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict + +from litex.soc.interconnect import axi +from litex.soc.interconnect import wishbone + +from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(Module): + def __init__(self, platform, sys_clk_freq, use_ps7_clk=False): + self.rst = Signal() + self.clock_domains.cd_sys = ClockDomain() + + # # # + + if use_ps7_clk: + assert sys_clk_freq == 100e6 + self.comb += ClockSignal("sys").eq(ClockSignal("ps7")) + self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst) + else: + self.submodules.pll = pll = S7PLL(speedgrade=-1) + self.comb += pll.reset.eq(self.rst) # ensure that ethernet is connected otherwise the CPU will reset every 2-3 seconds + pll.register_clkin(platform.request("clk125"), 125e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. + +# BaseSoC ------------------------------------------------------------------------------------------ + +class BaseSoC(SoCCore): + def __init__(self, sys_clk_freq=int(100e6), **kwargs): + platform = pynq_z2.Platform() + + if kwargs["uart_name"] == "serial": kwargs["uart_name"] = "usb_uart" # Use USB-UART Pmod on JB. + + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Pynq Z2", + ident_version = True, + **kwargs) + + # Zynq7000 Integration --------------------------------------------------------------------- + if kwargs.get("cpu_type", None) == "zynq7000": + # Get and set the pre-generated .xci FIXME: change location? add it to the repository? + os.system("wget https://github.com/litex-hub/litex-boards/files/4967144/zybo_z7_ps7.txt") + os.makedirs("xci", exist_ok=True) + os.system("mv zybo_z7_ps7.txt xci/zybo_z7_ps7.xci") + self.cpu.set_ps7_xci("xci/zybo_z7_ps7.xci") + + # Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one) + wb_gp0 = wishbone.Interface() + self.submodules += axi.AXI2Wishbone( + axi = self.cpu.add_axi_gp_master(), + wishbone = wb_gp0, + base_address = 0x43c00000) + self.add_wb_master(wb_gp0) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, sys_clk_freq) + + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) + +# Build -------------------------------------------------------------------------------------------- + +def main(): + parser = argparse.ArgumentParser(description="LiteX SoC on Pynq Z2") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") + builder_args(parser) + soc_core_args(parser) + vivado_build_args(parser) + args = parser.parse_args() + + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + **soc_core_argdict(args) + ) + builder = Builder(soc, **builder_argdict(args)) + builder.build(**vivado_build_argdict(args), run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"), device=1) + +if __name__ == "__main__": + main()