diff --git a/litex_boards/targets/1bitsquared_icebreaker.py b/litex_boards/targets/1bitsquared_icebreaker.py
index cd8e0ca..0dd889e 100755
--- a/litex_boards/targets/1bitsquared_icebreaker.py
+++ b/litex_boards/targets/1bitsquared_icebreaker.py
@@ -26,7 +26,6 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 from litex_boards.platforms import icebreaker
 
 from litex.soc.cores.ram import Up5kSPRAM
-from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.cores.clock import iCE40PLL
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc import SoCRegion
diff --git a/litex_boards/targets/1bitsquared_icebreaker_bitsy.py b/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
index 3c0a885..beed298 100755
--- a/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
+++ b/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
@@ -25,7 +25,6 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 from litex_boards.platforms import icebreaker_bitsy
 
 from litex.soc.cores.ram import Up5kSPRAM
-from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.cores.clock import iCE40PLL
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc import SoCRegion
diff --git a/litex_boards/targets/colorlight_i5.py b/litex_boards/targets/colorlight_i5.py
index 8aabdf6..bb4a08d 100755
--- a/litex_boards/targets/colorlight_i5.py
+++ b/litex_boards/targets/colorlight_i5.py
@@ -19,7 +19,6 @@ from litex_boards.platforms import colorlight_i5
 from litex.build.lattice.trellis import trellis_args, trellis_argdict
 
 from litex.soc.cores.clock import *
-from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
 from litex.soc.cores.video import VideoECP5HDMIPHY
diff --git a/litex_boards/targets/digilent_cmod_a7.py b/litex_boards/targets/digilent_cmod_a7.py
index a8b0473..736c40d 100755
--- a/litex_boards/targets/digilent_cmod_a7.py
+++ b/litex_boards/targets/digilent_cmod_a7.py
@@ -17,7 +17,6 @@ from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
 from litex_boards.platforms import digilent_cmod_a7
 
-#from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc import SoCRegion
diff --git a/litex_boards/targets/digilent_nexys4.py b/litex_boards/targets/digilent_nexys4.py
index b077588..6cb8f1d 100755
--- a/litex_boards/targets/digilent_nexys4.py
+++ b/litex_boards/targets/digilent_nexys4.py
@@ -17,7 +17,6 @@ from litex.build.io import CRG
 
 from litex_boards.platforms import digilent_nexys4
 
-#from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc import SoCRegion
diff --git a/litex_boards/targets/kosagi_fomu.py b/litex_boards/targets/kosagi_fomu.py
index 4751fc7..2e78d17 100755
--- a/litex_boards/targets/kosagi_fomu.py
+++ b/litex_boards/targets/kosagi_fomu.py
@@ -18,7 +18,6 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 from litex_boards.platforms import fomu_pvt
 
 from litex.soc.cores.ram import Up5kSPRAM
-from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.cores.clock import iCE40PLL
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc import SoCRegion
diff --git a/litex_boards/targets/lattice_crosslink_nx_evn.py b/litex_boards/targets/lattice_crosslink_nx_evn.py
index 878cebe..799597d 100755
--- a/litex_boards/targets/lattice_crosslink_nx_evn.py
+++ b/litex_boards/targets/lattice_crosslink_nx_evn.py
@@ -17,7 +17,6 @@ from litex_boards.platforms import crosslink_nx_evn
 
 from litex.soc.cores.ram import NXLRAM
 from litex.soc.cores.clock import NXPLL
-from litex.soc.cores.spi_flash import SpiFlash
 from litex.build.io import CRG
 from litex.build.generic_platform import *
 
diff --git a/litex_boards/targets/lattice_crosslink_nx_vip.py b/litex_boards/targets/lattice_crosslink_nx_vip.py
index c639a15..557c1d9 100755
--- a/litex_boards/targets/lattice_crosslink_nx_vip.py
+++ b/litex_boards/targets/lattice_crosslink_nx_vip.py
@@ -22,7 +22,6 @@ from litex_boards.platforms import crosslink_nx_vip
 from litehyperbus.core.hyperbus import HyperRAM
 
 from litex.soc.cores.ram import NXLRAM
-from litex.soc.cores.spi_flash import SpiFlash
 from litex.build.io import CRG
 from litex.build.generic_platform import *
 
diff --git a/litex_boards/targets/lattice_ice40up5k_evn.py b/litex_boards/targets/lattice_ice40up5k_evn.py
index dad5e6d..feba4fc 100755
--- a/litex_boards/targets/lattice_ice40up5k_evn.py
+++ b/litex_boards/targets/lattice_ice40up5k_evn.py
@@ -21,7 +21,6 @@ from litex_boards.platforms import lattice_ice40up5k_evn
 from litex.build.lattice.programmer import IceStormProgrammer
 
 from litex.soc.cores.ram import Up5kSPRAM
-from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.cores.clock import iCE40PLL
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc import SoCRegion
diff --git a/litex_boards/targets/micronova_mercury2.py b/litex_boards/targets/micronova_mercury2.py
index 3f3b26e..824b297 100755
--- a/litex_boards/targets/micronova_mercury2.py
+++ b/litex_boards/targets/micronova_mercury2.py
@@ -17,7 +17,6 @@ from litex.build.io import CRG
 from litex_boards.platforms import micronova_mercury2
 from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
-#from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc import SoCRegion
diff --git a/litex_boards/targets/muselab_icesugar_pro.py b/litex_boards/targets/muselab_icesugar_pro.py
index e46fef9..ba6cd19 100755
--- a/litex_boards/targets/muselab_icesugar_pro.py
+++ b/litex_boards/targets/muselab_icesugar_pro.py
@@ -19,7 +19,6 @@ from litex_boards.platforms import muselab_icesugar_pro
 from litex.build.lattice.trellis import trellis_args, trellis_argdict
 
 from litex.soc.cores.clock import *
-from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
 from litex.soc.cores.video import VideoECP5HDMIPHY
diff --git a/litex_boards/targets/tinyfpga_bx.py b/litex_boards/targets/tinyfpga_bx.py
index a841d03..af34aff 100755
--- a/litex_boards/targets/tinyfpga_bx.py
+++ b/litex_boards/targets/tinyfpga_bx.py
@@ -16,7 +16,6 @@ from litex.build.io import CRG
 
 from litex_boards.platforms import tinyfpga_bx
 
-from litex.soc.cores.spi_flash import SpiFlash
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *