From 55c0b781e4c71c7e29981e81e352ee5a91865966 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 23 Jan 2020 13:16:36 +0100 Subject: [PATCH] colorlight_5a_75b: revert rx_delay to 2ns, improve comment (thanks @tnt) --- litex_boards/partner/targets/colorlight_5a_75b.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/partner/targets/colorlight_5a_75b.py b/litex_boards/partner/targets/colorlight_5a_75b.py index 7ab9bf3..9e00715 100755 --- a/litex_boards/partner/targets/colorlight_5a_75b.py +++ b/litex_boards/partner/targets/colorlight_5a_75b.py @@ -68,8 +68,8 @@ class EtherboneSoC(BaseSoC): self.submodules.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks", eth_phy), pads = self.platform.request("eth", eth_phy), - tx_delay = 0e-9, # No FPGA delay (Clk/Data delay added by PCB/PHY) - rx_delay = 0e-9) # No FPGA delay (Clk/Data delay added by PCB/PHY) + tx_delay = 0e-9, # 0ns FPGA delay (Clk delay added by PHY) + rx_delay = 2e-9) # 2ns FPGA delay to compensate Clk routing to IDDRX1F self.add_csr("ethphy") # core self.submodules.ethcore = LiteEthUDPIPCore(