From 55ea71bd0199226e3e993fb7bd224b9c6d5d10ef Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 1 Sep 2021 19:21:16 +0200 Subject: [PATCH] gsd_butterstick: Add initial DDR3 support. Validated with: ./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load litex_server --udp litex_term bridge __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2021 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Sep 1 2021 19:09:52 BIOS CRC passed (3d349845) Migen git sha1: 27dbf03 LiteX git sha1: 315fbe18 --=============== SoC ==================-- CPU: VexRiscv @ 75MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 128KiB SRAM: 8KiB L2: 8KiB SDRAM: 524288KiB 16-bit @ 300MT/s (CL-6 CWL-5) --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Read leveling: m0, b00: |01110000| delays: 02+-01 m0, b01: |00000000| delays: - m0, b02: |00000000| delays: - m0, b03: |00000000| delays: - best: m0, b00 delays: 02+-01 m1, b00: |01110000| delays: 02+-01 m1, b01: |00000000| delays: - m1, b02: |00000000| delays: - m1, b03: |00000000| delays: - best: m1, b00 delays: 02+-01 Switching SDRAM to hardware control. Memtest at 0x40000000 (2.0MiB)... Write: 0x40000000-0x40200000 2.0MiB Read: 0x40000000-0x40200000 2.0MiB Memtest OK Memspeed at 0x40000000 (Sequential, 2.0MiB)... Write speed: 13.6MiB/s Read speed: 15.6MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex> --- litex_boards/platforms/gsd_butterstick.py | 26 +++++++++++ litex_boards/targets/gsd_butterstick.py | 53 +++++++++++++++++++++-- 2 files changed, 75 insertions(+), 4 deletions(-) diff --git a/litex_boards/platforms/gsd_butterstick.py b/litex_boards/platforms/gsd_butterstick.py index 9550eb0..c1c2849 100644 --- a/litex_boards/platforms/gsd_butterstick.py +++ b/litex_boards/platforms/gsd_butterstick.py @@ -29,6 +29,32 @@ _io_r1_0 = [ ("user_btn", 0, Pins("U16"), IOStandard("SSTL135_I")), ("user_btn", 1, Pins("T17"), IOStandard("SSTL135_I")), + # DDR3 SDRAM + ("ddram", 0, + Subsignal("a", Pins( + "G16 E19 E20 F16 F19 E16 F17 L20 " + "M20 E18 G18 D18 H18 C18 D17 G20 "), + IOStandard("SSTL135_I")), + Subsignal("ba", Pins("H16 F20 H20"), IOStandard("SSTL135_I")), + Subsignal("ras_n", Pins("K18"), IOStandard("SSTL135_I")), + Subsignal("cas_n", Pins("J17"), IOStandard("SSTL135_I")), + Subsignal("we_n", Pins("G19"), IOStandard("SSTL135_I")), + Subsignal("cs_n", Pins("J20 J16"), IOStandard("SSTL135_I")), + Subsignal("dm", Pins("U20 L18"), IOStandard("SSTL135_I")), + Subsignal("dq", Pins( + "U19 T18 U18 R20 P18 P19 P20 N20", + "L19 L17 L16 R16 N18 R17 N17 P17"), + IOStandard("SSTL135_I"), + Misc("TERMINATION=75")), + Subsignal("dqs_p", Pins("T19 N16"), IOStandard("SSTL135D_I"), + Misc("TERMINATION=OFF"), + Misc("DIFFRESISTOR=100")), + Subsignal("clk_p", Pins("C20 J19"), IOStandard("SSTL135D_I")), + Subsignal("cke", Pins("F18 J18"), IOStandard("SSTL135_I")), + Subsignal("odt", Pins("K20 H17"), IOStandard("SSTL135_I")), + Subsignal("reset_n", Pins("E17"), IOStandard("SSTL135_I")), + Misc("SLEWRATE=FAST") + ), # RGMII Ethernet ("eth_clocks", 0, diff --git a/litex_boards/targets/gsd_butterstick.py b/litex_boards/targets/gsd_butterstick.py index aecfb7d..f94fbed 100755 --- a/litex_boards/targets/gsd_butterstick.py +++ b/litex_boards/targets/gsd_butterstick.py @@ -17,6 +17,8 @@ import sys import argparse from migen import * +from migen.genlib.resetsync import AsyncResetSynchronizer + from litex_boards.platforms import butterstick from litex.build.lattice.trellis import trellis_args, trellis_argdict @@ -26,6 +28,9 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser +from litedram.modules import MT41K256M16 +from litedram.phy import ECP5DDRPHY + from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII # CRG --------------------------------------------------------------------------------------------- @@ -33,11 +38,17 @@ from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII class _CRG(Module): def __init__(self, platform, sys_clk_freq): self.rst = Signal() - self.clock_domains.cd_por = ClockDomain(reset_less=True) - self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_init = ClockDomain() + self.clock_domains.cd_por = ClockDomain(reset_less=True) + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys2x = ClockDomain() + self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True) # # # + self.stop = Signal() + self.reset = Signal() + # Clk / Rst clk30 = platform.request("clk30") rst_n = platform.request("user_btn", 0) @@ -50,10 +61,31 @@ class _CRG(Module): self.sync.por += If(~por_done, por_count.eq(por_count - 1)) # PLL + sys2x_clk_ecsout = Signal() self.submodules.pll = pll = ECP5PLL() self.comb += pll.reset.eq(~por_done | ~rst_n | self.rst) pll.register_clkin(clk30, 30e6) - pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq) + pll.create_clkout(self.cd_init, 25e6) + self.specials += [ + Instance("ECLKBRIDGECS", + i_CLK0 = self.cd_sys2x_i.clk, + i_SEL = 0, + o_ECSOUT = sys2x_clk_ecsout, + ), + Instance("ECLKSYNCB", + i_ECLKI = sys2x_clk_ecsout, + i_STOP = self.stop, + o_ECLKO = self.cd_sys2x.clk), + Instance("CLKDIVF", + p_DIV = "2.0", + i_ALIGNWD = 0, + i_CLKI = self.cd_sys2x.clk, + i_RST = self.reset, + o_CDIVX = self.cd_sys.clk), + AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), + AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset), + ] # BaseSoC ------------------------------------------------------------------------------------------ @@ -73,6 +105,19 @@ class BaseSoC(SoCCore): # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) + # DDR3 SDRAM ------------------------------------------------------------------------------- + if not self.integrated_main_ram_size: + self.submodules.ddrphy = ECP5DDRPHY( + platform.request("ddram"), + sys_clk_freq=sys_clk_freq) + self.comb += self.crg.stop.eq(self.ddrphy.init.stop) + self.comb += self.crg.reset.eq(self.ddrphy.init.reset) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT41K256M16(sys_clk_freq, "1:2"), + l2_cache_size = kwargs.get("l2_size", 8192) + ) + # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYRGMII( @@ -98,7 +143,7 @@ def main(): parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--toolchain", default="trellis", help="FPGA use, trellis (default) or diamond") - parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") + parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") parser.add_argument("--revision", default="1.0", help="Board Revision: 1.0 (default)") parser.add_argument("--device", default="85F", help="ECP5 device (default: 85F)") ethopts = parser.add_mutually_exclusive_group()