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qmtech_artix7_fgg676: fix wrong memory chip type

This commit is contained in:
Hans Baier 2024-03-29 08:28:02 +07:00
parent 2505aeb9b4
commit 5629f9e97a
2 changed files with 4 additions and 4 deletions
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4
litex_boards/targets/qmtech_artix7_fbg484.py
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@ -21,7 +21,7 @@ from litex.soc.integration.builder import *
from litex.soc.cores.video import VideoVGAPHY
from litex.soc.cores.led import LedChaser
from litedram.modules import MT41J128M16
from litedram.modules import MT41K128M16
from litedram.phy import s7ddrphy
from liteeth.phy.mii import LiteEthPHYMII
@ -100,7 +100,7 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J128M16(sys_clk_freq, "1:4"),
module = MT41K128M16(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192)
)

4
litex_boards/targets/qmtech_artix7_fgg676.py
View File

@ -21,7 +21,7 @@ from litex.soc.integration.builder import *
from litex.soc.cores.video import VideoVGAPHY
from litex.soc.cores.led import LedChaser
from litedram.modules import MT41J128M16
from litedram.modules import MT41K128M16
from litedram.phy import s7ddrphy
from liteeth.phy.mii import LiteEthPHYMII
@ -100,7 +100,7 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J128M16(sys_clk_freq, "1:4"),
module = MT41K128M16(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192)
)