From 566a753dd3ed980be0568df2279c3235f35bb790 Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Fri, 7 Apr 2023 08:45:06 +0700 Subject: [PATCH] stlv7325: S7PLL is enough --- litex_boards/targets/sitlinv_stlv7325.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/targets/sitlinv_stlv7325.py b/litex_boards/targets/sitlinv_stlv7325.py index dd9a0b6..6c063d8 100755 --- a/litex_boards/targets/sitlinv_stlv7325.py +++ b/litex_boards/targets/sitlinv_stlv7325.py @@ -59,7 +59,7 @@ class _CRG(LiteXModule): pll.create_clkout(self.cd_idelay, 200e6) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. - self.submodules.pll2 = pll2 = S7MMCM(speedgrade=-2) + self.submodules.pll2 = pll2 = S7PLL(speedgrade=-2) self.comb += pll2.reset.eq(~rst_n | self.rst) pll2.register_clkin(clk100, 100e6) pll2.create_clkout(self.cd_hdmi, 25e6, margin=0)