diff --git a/litex_boards/targets/alinx_axu2cga.py b/litex_boards/targets/alinx_axu2cga.py index e7f98a6..8f83767 100755 --- a/litex_boards/targets/alinx_axu2cga.py +++ b/litex_boards/targets/alinx_axu2cga.py @@ -74,10 +74,10 @@ class BaseSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- if kwargs.get("cpu_type", None) == "zynqmp": - kwargs['integrated_sram_size'] = 0 - kwargs['with_uart'] = False + kwargs["integrated_sram_size"] = 0 + kwargs["with_uart"] = False self.mem_map = { - 'csr': 0x8000_0000, # Zynq GP0 default + "csr": 0x8000_0000, # Zynq GP0 default } SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alinx AXU2CGA", **kwargs) @@ -90,7 +90,7 @@ class BaseSoC(SoCCore): self.submodules += axi.AXI2Wishbone( axi = self.cpu.add_axi_gp_master(2, 32), wishbone = wb_lpd, - base_address = self.mem_map['csr']) + base_address = self.mem_map["csr"]) self.bus.add_master(master=wb_lpd) self.bus.add_region("sram", SoCRegion( @@ -102,7 +102,7 @@ class BaseSoC(SoCCore): size = 512 * 1024 * 1024 // 8, linker = True) ) - self.constants['CONFIG_CLOCK_FREQUENCY'] = 1199880127 + self.constants["CONFIG_CLOCK_FREQUENCY"] = 1199880127 # Leds ------------------------------------------------------------------------------------- if with_led_chaser: diff --git a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py index 7d6b09a..7009194 100755 --- a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py +++ b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py @@ -167,7 +167,7 @@ class BaseSoC(SoCCore): class LiteDRAMSettingsEncoder(json.JSONEncoder): def default(self, o): if isinstance(o, (ControllerSettings, GeomSettings, PhySettings, TimingSettings)): - ignored = ['self', 'refresh_cls'] + ignored = ["self", "refresh_cls"] return {k: v for k, v in vars(o).items() if k not in ignored} elif isinstance(o, Signal) and isinstance(o.reset, Constant): return o.reset diff --git a/litex_boards/targets/digilent_arty_z7.py b/litex_boards/targets/digilent_arty_z7.py index def214d..67b996d 100755 --- a/litex_boards/targets/digilent_arty_z7.py +++ b/litex_boards/targets/digilent_arty_z7.py @@ -61,8 +61,8 @@ class BaseSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- if kwargs.get("cpu_type", None) == "zynq7000": - kwargs['integrated_sram_size'] = 0 - kwargs['with_uart'] = False + kwargs["integrated_sram_size"] = 0 + kwargs["with_uart"] = False self.mem_map = { 'csr': 0x4000_0000, # Zynq GP0 default } @@ -82,7 +82,7 @@ class BaseSoC(SoCCore): self.submodules += axi.AXI2Wishbone( axi = self.cpu.add_axi_gp_master(), wishbone = wb_gp0, - base_address = self.mem_map['csr']) + base_address = self.mem_map["csr"]) self.bus.add_master(master=wb_gp0) # Leds ------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/digilent_zedboard.py b/litex_boards/targets/digilent_zedboard.py index 4024066..430e888 100755 --- a/litex_boards/targets/digilent_zedboard.py +++ b/litex_boards/targets/digilent_zedboard.py @@ -78,15 +78,15 @@ class BaseSoC(SoCCore): self.bus.add_master(master=wb_gp0) self.bus.add_region("sram", SoCRegion( - origin=self.cpu.mem_map["sram"], - size=512 * 1024 * 1024 - self.cpu.mem_map["sram"]) + origin = self.cpu.mem_map["sram"], + size = 512 * 1024 * 1024 - self.cpu.mem_map["sram"]) ) self.bus.add_region("rom", SoCRegion( - origin=self.cpu.mem_map["rom"], - size=256 * 1024 * 1024 // 8, - linker=True) + origin = self.cpu.mem_map["rom"], + size = 256 * 1024 * 1024 // 8, + linker = True) ) - self.constants['CONFIG_CLOCK_FREQUENCY'] = 666666687 + self.constants["CONFIG_CLOCK_FREQUENCY"] = 666666687 # Leds ------------------------------------------------------------------------------------- if with_led_chaser: diff --git a/litex_boards/targets/krtkl_snickerdoodle.py b/litex_boards/targets/krtkl_snickerdoodle.py index 55bea1d..9745627 100755 --- a/litex_boards/targets/krtkl_snickerdoodle.py +++ b/litex_boards/targets/krtkl_snickerdoodle.py @@ -92,7 +92,7 @@ class BaseSoC(SoCCore): self.submodules += axi.AXI2Wishbone( axi = self.cpu.add_axi_gp_master(), wishbone = wb_gp0, - base_address = self.mem_map['csr']) + base_address = self.mem_map["csr"]) self.bus.add_master(master=wb_gp0) # Leds ------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/quicklogic_quickfeather.py b/litex_boards/targets/quicklogic_quickfeather.py index 7c0d8ab..d627298 100755 --- a/litex_boards/targets/quicklogic_quickfeather.py +++ b/litex_boards/targets/quicklogic_quickfeather.py @@ -54,7 +54,7 @@ class BaseSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- kwargs["with_uart"] = False if kwargs.get("cpu_type", None) == "eos_s3": - kwargs['integrated_sram_size'] = 0 + kwargs["integrated_sram_size"] = 0 SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on QuickLogic QuickFeather", **kwargs) # EOS-S3 Integration ----------------------------------------------------------------------- diff --git a/litex_boards/targets/xilinx_kv260.py b/litex_boards/targets/xilinx_kv260.py index ceaf8d7..5e8cf13 100755 --- a/litex_boards/targets/xilinx_kv260.py +++ b/litex_boards/targets/xilinx_kv260.py @@ -66,7 +66,7 @@ class BaseSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- if kwargs.get("cpu_type", None) == "zynqmp": - kwargs['integrated_sram_size'] = 0 + kwargs["integrated_sram_size"] = 0 SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on KV260", **kwargs) # ZynqMP Integration ----------------------------------------------------------------------- @@ -134,15 +134,15 @@ class BaseSoC(SoCCore): base_address = self.mem_map["csr"]) self.bus.add_master(master=wb_gp0) self.bus.add_region("sram", SoCRegion( - origin=self.cpu.mem_map["sram"], - size=2 * 1024 * 1024 * 1024) # DDR + origin = self.cpu.mem_map["sram"], + size = 2 * 1024 * 1024 * 1024) # DDR ) self.bus.add_region("rom", SoCRegion( - origin=self.cpu.mem_map["rom"], - size=512 * 1024 * 1024 // 8, - linker=True) + origin = self.cpu.mem_map["rom"], + size = 512 * 1024 * 1024 // 8, + linker = True) ) - self.constants['CONFIG_CLOCK_FREQUENCY'] = 1333333008 + self.constants["CONFIG_CLOCK_FREQUENCY"] = 1333333008 def finalize(self, *args, **kwargs): super(BaseSoC, self).finalize(*args, **kwargs) diff --git a/litex_boards/targets/xilinx_zcu216.py b/litex_boards/targets/xilinx_zcu216.py index 670f4d2..bc934fd 100755 --- a/litex_boards/targets/xilinx_zcu216.py +++ b/litex_boards/targets/xilinx_zcu216.py @@ -55,7 +55,7 @@ class BaseSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- if kwargs.get("cpu_type", None) == "zynqmp": - kwargs['integrated_sram_size'] = 0 + kwargs["integrated_sram_size"] = 0 SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZCU216", **kwargs) # ZynqMP Integration ----------------------------------------------------------------------- @@ -122,7 +122,7 @@ class BaseSoC(SoCCore): size = 512 * 1024 * 1024 // 8, linker = True) ) - self.constants['CONFIG_CLOCK_FREQUENCY'] = 1200000000 + self.constants["CONFIG_CLOCK_FREQUENCY"] = 1200000000 # LEDs ------------------------------------------------------------------------------------- if with_led_chaser: