From 57a9970257c0521bfdabe5a871cc4babbe8efd6b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 27 Mar 2024 08:49:40 +0100 Subject: [PATCH] xilinx_zc706: ADD DDR3 support in target and update/fix IOs definition in platform (Untested on hardware). - Use/Mimic IO standards from KC705. - Keep it to single rank for now (but add dual rank IOs in comments). - Add DCI cascade property. - Add sys4x and idelay clocking. - Add LiteDRAM PHY/Core support. --- litex_boards/platforms/xilinx_zc706.py | 35 ++++++++++++++------------ litex_boards/targets/xilinx_zc706.py | 35 ++++++++++++++++++++++---- 2 files changed, 49 insertions(+), 21 deletions(-) diff --git a/litex_boards/platforms/xilinx_zc706.py b/litex_boards/platforms/xilinx_zc706.py index 388176e..bcee6a9 100644 --- a/litex_boards/platforms/xilinx_zc706.py +++ b/litex_boards/platforms/xilinx_zc706.py @@ -57,17 +57,18 @@ _io = [ ), # DDR3 SDRAM. - ("ddram", 0 + ("ddram", 0, Subsignal("a", Pins( "E10 B9 E11 A9 D11 B6 F9 E8", "B10 J8 D6 B7 H12 A10 G11 C6"), IOStandard("SSTL15")), - Subsignal("ba", Pins("F8 H7 A7"), IOStandard("SSTL15")), - Subsignal("ras_n", Pins("H11"), IOStandard("SSTL15")), - Subsignal("cas_n", Pins("E7"), IOStandard("SSTL15")), - Subsignal("we_n", Pins("F7"), IOStandard("SSTL15")), - Subsignal("cs_n", Pins("J11 H8"), IOStandard("SSTL15")), - Subsignal("dm", Pins("J3 F2 E1 C2 L12 G14 C16 C11"), + Subsignal("ba", Pins("F8 H7 A7"), IOStandard("SSTL15")), + Subsignal("ras_n", Pins("H11"), IOStandard("SSTL15")), + Subsignal("cas_n", Pins("E7"), IOStandard("SSTL15")), + Subsignal("we_n", Pins("F7"), IOStandard("SSTL15")), + Subsignal("cs_n", Pins("J11"), IOStandard("SSTL15")), # J11 H8 + Subsignal("dm", Pins( + "J3 F2 E1 C2 L12 G14 C16 C11"), IOStandard("SSTL15")), Subsignal("dq", Pins( " L1 L2 K5 J4 K1 L3 J5 K6", @@ -77,18 +78,19 @@ _io = [ "K10 L9 K12 J9 K11 L10 J10 L7", "F14 F15 F13 G16 G15 E12 D13 E13", "D15 E15 D16 E16 C17 B16 D14 B17", - "B12 C12 A12 A14 A13 B11 C14 B14", - IOStandard("SSTL15")), + "B12 C12 A12 A14 A13 B11 C14 B14"), + IOStandard("SSTL15_T_DCI")), Subsignal("dqs_p", Pins("K3 J1 E6 A5 L8 G12 F17 B15"), - IOStandard("SSTL15")), + IOStandard("DIFF_SSTL15")), Subsignal("dqs_n", Pins("K2 H1 D5 A4 K8 F12 E17 A15"), - IOStandard("SSTL15")), - Subsignal("clk_p", Pins("G10 D9"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_n", Pins("F10 D8"), IOStandard("DIFF_SSTL15")), - Subsignal("cke", Pins("D10 C7"), IOStandard("SSTL15")), - Subsignal("odt", Pins("G7 C9"), IOStandard("SSTL15")), - Subsignal("reset_n", Pins("G17"), IOStandard("LVCMOS15")), + IOStandard("DIFF_SSTL15")), + Subsignal("clk_p", Pins("G10"), IOStandard("DIFF_SSTL15")), # G10 D9 + Subsignal("clk_n", Pins("F10"), IOStandard("DIFF_SSTL15")), # F10 D8 + Subsignal("cke", Pins("D10"), IOStandard("SSTL15")), # D10 C7 + Subsignal("odt", Pins("G7"), IOStandard("SSTL15")), # G7 C9 + Subsignal("reset_n", Pins("G17"), IOStandard("LVCMOS15")), Misc("SLEW=FAST"), + Misc("VCCAUX_IO=HIGH") ), # PCIe. @@ -391,3 +393,4 @@ class Platform(Xilinx7SeriesPlatform): def do_finalize(self, fragment): Xilinx7SeriesPlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6) + self.add_platform_command("set_property DCI_CASCADE {{34}} [get_iobanks 33]") diff --git a/litex_boards/targets/xilinx_zc706.py b/litex_boards/targets/xilinx_zc706.py index 2593b94..ff589a3 100755 --- a/litex_boards/targets/xilinx_zc706.py +++ b/litex_boards/targets/xilinx_zc706.py @@ -30,6 +30,9 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser +from litedram.modules import MT8JTF12864 +from litedram.phy import s7ddrphy + from liteeth.phy.k7_1000basex import K7_1000BASEX from litepcie.phy.s7pciephy import S7PCIEPHY @@ -39,9 +42,11 @@ from litepcie.software import generate_litepcie_software class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): - self.rst = Signal() - self.cd_sys = ClockDomain() - self.cd_eth = ClockDomain() + self.rst = Signal() + self.cd_sys = ClockDomain() + self.cd_sys4x = ClockDomain() + self.cd_idelay = ClockDomain() + self.cd_eth = ClockDomain() # # # @@ -52,10 +57,15 @@ class _CRG(LiteXModule): self.pll = pll = S7PLL(speedgrade=-1) self.comb += pll.reset.eq(self.rst) pll.register_clkin(clk200, 200e6) - pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_eth, 200e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_idelay, 200e6) + pll.create_clkout(self.cd_eth, 200e6) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. + # IDelayCtrl. + self.idelayctrl = S7IDELAYCTRL(self.cd_idelay) + # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): @@ -78,6 +88,18 @@ class BaseSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZCU706", **kwargs) + # DDR3 SDRAM ------------------------------------------------------------------------------- + if not self.integrated_main_ram_size: + self.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), + memtype = "DDR3", + nphases = 4, + sys_clk_freq = sys_clk_freq) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT8JTF12864(sys_clk_freq, "1:4"), + l2_cache_size = kwargs.get("l2_size", 8192) + ) + # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.ethphy = K7_1000BASEX( @@ -135,6 +157,9 @@ def main(): if args.build: builder.build(**parser.toolchain_argdict) + if args.driver: + generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver")) + if args.load: prog = soc.platform.create_programmer() prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))