From 591377cf95bcf9732fa9b55171394744c44cf9b3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 25 Jun 2021 11:18:55 +0200 Subject: [PATCH] decklink: Pinout fixes on itensity_pro_4k and quad_hdm_recorder. --- .../platforms/decklink_intensity_pro_4k.py | 14 ++++++++------ .../platforms/decklink_quad_hdmi_recorder.py | 4 ++++ 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/litex_boards/platforms/decklink_intensity_pro_4k.py b/litex_boards/platforms/decklink_intensity_pro_4k.py index 6a919e1..5b41541 100644 --- a/litex_boards/platforms/decklink_intensity_pro_4k.py +++ b/litex_boards/platforms/decklink_intensity_pro_4k.py @@ -16,13 +16,13 @@ _io = [ # TODO. # Debug. - ("debug", 0, Pins("R22"), IOStandard("LVCMOS33")), - ("debug", 1, Pins("P21"), IOStandard("LVCMOS33")), - ("debug", 2, Pins("P23"), IOStandard("LVCMOS33")), - ("debug", 3, Pins("N23"), IOStandard("LVCMOS33")), + ("debug", 0, Pins("A15"), IOStandard("LVCMOS33")), + ("debug", 1, Pins("C14"), IOStandard("LVCMOS33")), + ("debug", 2, Pins("B14"), IOStandard("LVCMOS33")), + ("debug", 3, Pins("A14"), IOStandard("LVCMOS33")), # Fan. - ("fan", 0, Pins("K18"), IOStandard("LVCMOS33")), + ("fan", 0, Pins(""), IOStandard("LVCMOS33")), # Flash. ("flash_cs_n", 0, Pins("C23"), IOStandard("LVCMOS33")), @@ -36,7 +36,7 @@ _io = [ # PCIe. ("pcie_x4", 0, - Subsignal("rst_n", Pins("K15"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), + Subsignal("rst_n", Pins("K21"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), Subsignal("clk_p", Pins("K6")), Subsignal("clk_n", Pins("K5")), Subsignal("rx_p", Pins("J4 L4 N4 R4")), @@ -45,6 +45,8 @@ _io = [ Subsignal("tx_n", Pins("H1 K1 M1 P1")) ), + # DRAM (MT47H64M16). + # HDMI Out. # TODO. diff --git a/litex_boards/platforms/decklink_quad_hdmi_recorder.py b/litex_boards/platforms/decklink_quad_hdmi_recorder.py index 393d759..f319ace 100644 --- a/litex_boards/platforms/decklink_quad_hdmi_recorder.py +++ b/litex_boards/platforms/decklink_quad_hdmi_recorder.py @@ -56,6 +56,10 @@ _io = [ Subsignal("tx_n", Pins("AC3 AE3 AG3 AH5 AK5 AL3 AM5 AN3")) ), + # DRAM (H5TQ4G63CFR). + + # TODO. + # HDMI (through PI3HDX1204) ("hdmi_in", 0, # PCIe Edge Side. #Subsignal("clk_p", Pins(""), IOStandard("")),