From 5955a35372bf24bf34d03139b040c4061559d441 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 16 Sep 2021 19:22:30 +0200 Subject: [PATCH] Add initial Sipeed Tang Nano support (Clk/Leds/Buttons). --- litex_boards/platforms/sipeed_tang_nano.py | 51 ++++++++++++ litex_boards/targets/sipeed_tang_nano.py | 91 +++++++++++++++++++++ litex_boards/targets/sipeed_tang_nano_4k.py | 1 + 3 files changed, 143 insertions(+) create mode 100644 litex_boards/platforms/sipeed_tang_nano.py create mode 100755 litex_boards/targets/sipeed_tang_nano.py diff --git a/litex_boards/platforms/sipeed_tang_nano.py b/litex_boards/platforms/sipeed_tang_nano.py new file mode 100644 index 0000000..15a6525 --- /dev/null +++ b/litex_boards/platforms/sipeed_tang_nano.py @@ -0,0 +1,51 @@ +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2021 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +# Board diagram/pinout: +# https://user-images.githubusercontent.com/1450143/133655492-532d5e9a-0635-4889-85c9-68683d06cae0.png +# http://dl.sipeed.com/TANG/Nano/HDK/Tang-NANO-2704(Schematic).pdf + +from migen import * + +from litex.build.generic_platform import * +from litex.build.gowin.platform import GowinPlatform +from litex.build.openfpgaloader import OpenFPGALoader + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + # Clk / Rst + ("clk24", 0, Pins("35"), IOStandard("LVCMOS33")), + + # Leds + ("user_led", 0, Pins("16"), IOStandard("LVCMOS33")), + ("user_led", 1, Pins("17"), IOStandard("LVCMOS33")), + ("user_led", 2, Pins("18"), IOStandard("LVCMOS33")), + + # Buttons. + ("user_btn", 0, Pins("15"), IOStandard("LVCMOS18")), + ("user_btn", 0, Pins("14"), IOStandard("LVCMOS18")), +] + +# Connectors --------------------------------------------------------------------------------------- + +_connectors = [] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(GowinPlatform): + default_clk_name = "clk24" + default_clk_period = 1e9/24e6 + + def __init__(self): + GowinPlatform.__init__(self, "GW1N-LV1QN48C6/I5", _io, _connectors, toolchain="gowin", devicename="GW1N-1") + + def create_programmer(self): + return OpenFPGALoader("tangnano") + + def do_finalize(self, fragment): + GowinPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk24", loose=True), 1e9/24e6) diff --git a/litex_boards/targets/sipeed_tang_nano.py b/litex_boards/targets/sipeed_tang_nano.py new file mode 100755 index 0000000..b955e3f --- /dev/null +++ b/litex_boards/targets/sipeed_tang_nano.py @@ -0,0 +1,91 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2021 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +import os +import argparse + +from migen import * +from migen.genlib.resetsync import AsyncResetSynchronizer + +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser + +from litex_boards.platforms import tang_nano + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(Module): + def __init__(self, platform, sys_clk_freq): + self.rst = Signal() + self.clock_domains.cd_sys = ClockDomain() + + # # # + + # Clk / Rst + clk24 = platform.request("clk24") + rst_n = platform.request("user_btn", 0) + self.comb += self.cd_sys.clk.eq(clk24) + self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n) + +# BaseSoC ------------------------------------------------------------------------------------------ + +class BaseSoC(SoCCore): + def __init__(self, sys_clk_freq=int(24e6), with_led_chaser=True, **kwargs): + platform = tang_nano.Platform() + + + # Disable CPU/UART for now. + kwargs["cpu_type"] = None + kwargs["with_uart"] = False + + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Tang Nano", + ident_version = True, + **kwargs) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, sys_clk_freq) + + # Leds ------------------------------------------------------------------------------------- + if with_led_chaser: + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) + +# Build -------------------------------------------------------------------------------------------- + +def main(): + parser = argparse.ArgumentParser(description="LiteX SoC on Tang Nano") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--flash", action="store_true", help="Flash Bitstream") + parser.add_argument("--sys-clk-freq",default=24e6, help="System clock frequency (default: 24MHz)") + builder_args(parser) + soc_core_args(parser) + args = parser.parse_args() + + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + **soc_core_argdict(args) + ) + + builder = Builder(soc, **builder_argdict(args)) + builder.build(run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs")) + + if args.flash: + prog = soc.platform.create_programmer() + prog.flash(0, os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs")) + +if __name__ == "__main__": + main() diff --git a/litex_boards/targets/sipeed_tang_nano_4k.py b/litex_boards/targets/sipeed_tang_nano_4k.py index 6d2ea4a..2172861 100755 --- a/litex_boards/targets/sipeed_tang_nano_4k.py +++ b/litex_boards/targets/sipeed_tang_nano_4k.py @@ -17,6 +17,7 @@ from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser from litex_boards.platforms import tang_nano_4k + # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module):