From dd134a4b7dd9e336e32410a333bc1ea23ec68ebb Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Wed, 26 Jan 2022 07:30:06 +0100 Subject: [PATCH] digilent arty z7: allows toolchain selection (PL only) --- litex_boards/platforms/digilent_arty_z7.py | 4 ++-- litex_boards/targets/digilent_arty_z7.py | 13 +++++++++---- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/litex_boards/platforms/digilent_arty_z7.py b/litex_boards/platforms/digilent_arty_z7.py index e53eaad..e175358 100644 --- a/litex_boards/platforms/digilent_arty_z7.py +++ b/litex_boards/platforms/digilent_arty_z7.py @@ -224,7 +224,7 @@ class Platform(XilinxPlatform): default_clk_name = "clk125" default_clk_freq = 125e6 - def __init__(self, variant="z7-20"): + def __init__(self, variant="z7-20", toolchain="vivado"): device = { "z7-10": "xc7z010clg400-1", "z7-20": "xc7z020clg400-1" @@ -235,7 +235,7 @@ class Platform(XilinxPlatform): }[variant] XilinxPlatform.__init__(self, device, _io, _connectors, - toolchain="vivado") + toolchain=toolchain) self.default_clk_period = 1e9 / self.default_clk_freq def create_programmer(self): diff --git a/litex_boards/targets/digilent_arty_z7.py b/litex_boards/targets/digilent_arty_z7.py index 92a8b6e..e91a392 100755 --- a/litex_boards/targets/digilent_arty_z7.py +++ b/litex_boards/targets/digilent_arty_z7.py @@ -50,8 +50,9 @@ class _CRG(Module): class BaseSoC(SoCCore): - def __init__(self, variant="z7-20", sys_clk_freq=int(125e6), with_led_chaser=True, **kwargs): - platform = digilent_arty_z7.Platform(variant) + def __init__(self, variant="z7-20", toolchain="vivado", sys_clk_freq=int(125e6), + with_led_chaser=True, **kwargs): + platform = digilent_arty_z7.Platform(variant=variant, toolchain=toolchain) if kwargs.get("cpu_type", None) == "zynq7000": kwargs['integrated_sram_size'] = 0 @@ -67,6 +68,8 @@ class BaseSoC(SoCCore): # Zynq7000 Integration --------------------------------------------------------------------- if kwargs.get("cpu_type", None) == "zynq7000": + assert toolchain == "vivado", ' not tested / specific vivado cmds' + preset_name = "arty_z7_20.tcl" if variant == "z7-20" else "arty_z7_10.tcl" os.system("wget http://kmf2.trabucayre.com/" + preset_name) @@ -97,6 +100,7 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Arty Z7") + parser.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado, symbiflow or yosys+nextpnr).") parser.add_argument("--build", action="store_true", help="Build bitstream.") parser.add_argument("--load", action="store_true", help="Load bitstream.") parser.add_argument("--variant", default="z7-20", help="Board variant (z7-20 or z7-10).") @@ -109,12 +113,13 @@ def main(): soc = BaseSoC( variant = args.variant, + toolchain = args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) - print(builder.compile_software) - builder.build(**vivado_build_argdict(args), run=args.build) + builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {} + builder.build(**builder_kwargs, run=args.build) if args.load: prog = soc.platform.create_programmer()