From 5995769b46f9f37ad916b74cbaad12d11a71f9af Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 24 Mar 2021 15:01:23 +0100 Subject: [PATCH] targets: Switch to soc_core_args/soc_core_argdict (instead of soc_sdram that is now deprecated, but still supported for now). --- litex_boards/targets/ac701.py | 5 ++--- litex_boards/targets/acorn_cle_215.py | 5 ++--- litex_boards/targets/aller.py | 5 ++--- litex_boards/targets/alveo_u250.py | 5 ++--- litex_boards/targets/alveo_u280.py | 5 ++--- litex_boards/targets/arrow_sockit.py | 11 +++++------ litex_boards/targets/arty.py | 5 ++--- litex_boards/targets/arty_s7.py | 5 ++--- litex_boards/targets/c10lprefkit.py | 5 ++--- litex_boards/targets/camlink_4k.py | 5 ++--- litex_boards/targets/de0nano.py | 5 ++--- litex_boards/targets/de10lite.py | 5 ++--- litex_boards/targets/de10nano.py | 5 ++--- litex_boards/targets/de1soc.py | 5 ++--- litex_boards/targets/de2_115.py | 5 ++--- litex_boards/targets/deca.py | 5 ++--- litex_boards/targets/fpc_iii.py | 5 ++--- litex_boards/targets/genesys2.py | 5 ++--- litex_boards/targets/hadbadge.py | 5 ++--- litex_boards/targets/kc705.py | 5 ++--- litex_boards/targets/kcu105.py | 5 ++--- litex_boards/targets/kx2.py | 5 ++--- litex_boards/targets/linsn_rv901t.py | 5 ++--- litex_boards/targets/litefury.py | 5 ++--- litex_boards/targets/logicbone.py | 5 ++--- litex_boards/targets/mercury_xu5.py | 5 ++--- litex_boards/targets/mimas_a7.py | 5 ++--- litex_boards/targets/minispartan6.py | 5 ++--- litex_boards/targets/mist.py | 5 ++--- litex_boards/targets/nereid.py | 5 ++--- litex_boards/targets/netv2.py | 5 ++--- litex_boards/targets/nexys4ddr.py | 5 ++--- litex_boards/targets/nexys_video.py | 5 ++--- litex_boards/targets/orangecrab.py | 5 ++--- litex_boards/targets/pipistrello.py | 5 ++--- litex_boards/targets/qmtech_ep4ce15.py | 5 ++--- litex_boards/targets/qmtech_wukong.py | 9 ++++----- litex_boards/targets/sds1104xe.py | 5 ++--- litex_boards/targets/tagus.py | 5 ++--- litex_boards/targets/trellisboard.py | 7 +++---- litex_boards/targets/ulx3s.py | 5 ++--- litex_boards/targets/vc707.py | 5 ++--- litex_boards/targets/vcu118.py | 5 ++--- litex_boards/targets/versa_ecp5.py | 5 ++--- litex_boards/targets/xcu1525.py | 5 ++--- litex_boards/targets/zcu104.py | 5 ++--- litex_boards/targets/ztex213.py | 5 ++--- 47 files changed, 100 insertions(+), 147 deletions(-) diff --git a/litex_boards/targets/ac701.py b/litex_boards/targets/ac701.py index d6deea6..d864ebc 100755 --- a/litex_boards/targets/ac701.py +++ b/litex_boards/targets/ac701.py @@ -16,7 +16,6 @@ from litex_boards.platforms import ac701 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -143,7 +142,7 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on AC701") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") @@ -158,7 +157,7 @@ def main(): with_ethernet = args.with_ethernet, eth_phy = args.eth_phy, with_pcie = args.with_pcie, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py index 27b55d4..5144b45 100755 --- a/litex_boards/targets/acorn_cle_215.py +++ b/litex_boards/targets/acorn_cle_215.py @@ -33,7 +33,6 @@ from litex_boards.platforms import acorn_cle_215 from litex.soc.interconnect.csr import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.clock import * @@ -166,14 +165,14 @@ def main(): parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support (requires SDCard adapter on P2)") pcieopts.add_argument("--with-sata", action="store_true", help="Enable SATA support (over PCIe2SATA)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), with_pcie = args.with_pcie, with_sata = args.with_sata, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) if args.with_spi_sdcard: soc.add_spi_sdcard() diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py index 1dd5e36..fbb8642 100755 --- a/litex_boards/targets/aller.py +++ b/litex_boards/targets/aller.py @@ -17,7 +17,6 @@ from litex_boards.platforms import aller from litex.soc.interconnect.csr import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.clock import * @@ -111,13 +110,13 @@ def main(): parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), with_pcie = args.with_pcie, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/alveo_u250.py b/litex_boards/targets/alveo_u250.py index a4a07df..8dd4d2c 100755 --- a/litex_boards/targets/alveo_u250.py +++ b/litex_boards/targets/alveo_u250.py @@ -17,7 +17,6 @@ from litex_boards.platforms import alveo_u250 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -116,13 +115,13 @@ def main(): parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), with_pcie = args.with_pcie, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/alveo_u280.py b/litex_boards/targets/alveo_u280.py index da230fb..d901762 100755 --- a/litex_boards/targets/alveo_u280.py +++ b/litex_boards/targets/alveo_u280.py @@ -16,7 +16,6 @@ from litex_boards.platforms import alveo_u280 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -117,14 +116,14 @@ def main(): parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), ddram_channel = int(args.ddram_channel, 0), with_pcie = args.with_pcie, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/arrow_sockit.py b/litex_boards/targets/arrow_sockit.py index d5b66d6..030a083 100755 --- a/litex_boards/targets/arrow_sockit.py +++ b/litex_boards/targets/arrow_sockit.py @@ -22,8 +22,7 @@ from migen.fhdl.structure import Signal, ClockDomain, ClockSignal from litex.soc.cores.clock import CycloneVPLL from litex.soc.integration.builder import Builder, builder_args, builder_argdict -from litex.soc.integration.soc_core import SoCCore -from litex.soc.integration.soc_sdram import soc_sdram_argdict, soc_sdram_args +from litex.soc.integration.soc_core import SoCCore, soc_core_argdict, soc_core_args from litex.soc.cores.led import LedChaser from litex.soc.cores.video import VideoVGAPHY @@ -44,7 +43,7 @@ class W9825G6KH6(SDRModule): I get a number of data errors if I run it at 50MHz, so this defaults to 1:2. If you want to use a higher system clock (eg 100MHz), you might want to consider - using 1:1 clocking, because the -6 speedgrade + using 1:1 clocking, because the -6 speedgrade can be clocked up to 166MHz (CL3) or 133MHz (CL2) """ # geometry @@ -158,7 +157,7 @@ class BaseSoC(SoCCore): l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_reverse = True ) - + # Video Terminal --------------------------------------------------------------------------- if with_video_terminal: vga_pads = platform.request("vga") @@ -180,7 +179,7 @@ def main(): parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( @@ -189,7 +188,7 @@ def main(): sdram_rate = "1:1" if args.single_rate_sdram else "1:2", mister_sdram = "xs_v22" if args.mister_sdram_xs_v22 else "xs_v24" if args.mister_sdram_xs_v24 else None, with_video_terminal = args.with_video_terminal, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/arty.py b/litex_boards/targets/arty.py index b278f3f..5a9064b 100755 --- a/litex_boards/targets/arty.py +++ b/litex_boards/targets/arty.py @@ -17,7 +17,6 @@ from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -127,7 +126,7 @@ def main(): parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output") parser.add_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) vivado_build_args(parser) args = parser.parse_args() @@ -143,7 +142,7 @@ def main(): eth_dynamic_ip = args.eth_dynamic_ip, ident_version = args.no_ident_version, with_jtagbone = args.with_jtagbone, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) if args.sdcard_adapter == "numato": soc.platform.add_extension(arty._numato_sdcard_pmod_io) diff --git a/litex_boards/targets/arty_s7.py b/litex_boards/targets/arty_s7.py index 65f56e7..97e1373 100755 --- a/litex_boards/targets/arty_s7.py +++ b/litex_boards/targets/arty_s7.py @@ -17,7 +17,6 @@ from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -96,14 +95,14 @@ def main(): parser.add_argument("--variant", default="s7-50", help="Board variant: s7-50 (default) or s7-25") parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) vivado_build_args(parser) args = parser.parse_args() soc = BaseSoC( variant = args.variant, sys_clk_freq = int(float(args.sys_clk_freq)), - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(**vivado_build_argdict(args), run=args.build) diff --git a/litex_boards/targets/c10lprefkit.py b/litex_boards/targets/c10lprefkit.py index 5259ec8..98a59e9 100755 --- a/litex_boards/targets/c10lprefkit.py +++ b/litex_boards/targets/c10lprefkit.py @@ -17,7 +17,6 @@ from litex_boards.platforms import c10lprefkit from litex.soc.cores.clock import Cyclone10LPPLL from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -112,13 +111,13 @@ def main(): parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), with_ethernet = args.with_ethernet, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/camlink_4k.py b/litex_boards/targets/camlink_4k.py index 12233f5..ab32980 100755 --- a/litex_boards/targets/camlink_4k.py +++ b/litex_boards/targets/camlink_4k.py @@ -18,7 +18,6 @@ from litex.build.lattice.trellis import trellis_args, trellis_argdict from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -119,14 +118,14 @@ def main(): parser.add_argument("--sys-clk-freq", default=81e6, help="System clock frequency (default: 81MHz)") parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) trellis_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), toolchain = args.toolchain, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} diff --git a/litex_boards/targets/de0nano.py b/litex_boards/targets/de0nano.py index 5dac1f0..730c9fe 100755 --- a/litex_boards/targets/de0nano.py +++ b/litex_boards/targets/de0nano.py @@ -18,7 +18,6 @@ from litex_boards.platforms import de0nano from litex.soc.cores.clock import CycloneIVPLL from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -101,13 +100,13 @@ def main(): parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), sdram_rate = args.sdram_rate, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/de10lite.py b/litex_boards/targets/de10lite.py index e5d3949..c0276d6 100755 --- a/litex_boards/targets/de10lite.py +++ b/litex_boards/targets/de10lite.py @@ -19,7 +19,6 @@ from litex_boards.platforms import de10lite from litex.soc.cores.clock import Max10PLL from litex.soc.integration.soc import SoCRegion from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.video import VideoVGAPHY from litex.soc.cores.led import LedChaser @@ -100,13 +99,13 @@ def main(): parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), with_video_terminal = args.with_video_terminal, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/de10nano.py b/litex_boards/targets/de10nano.py index 5b2e4e1..35d96f5 100755 --- a/litex_boards/targets/de10nano.py +++ b/litex_boards/targets/de10nano.py @@ -19,7 +19,6 @@ from litex_boards.platforms import de10nano from litex.soc.cores.clock import CycloneVPLL from litex.soc.integration.soc import SoCRegion from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.video import VideoVGAPHY from litex.soc.cores.led import LedChaser @@ -113,7 +112,7 @@ def main(): parser.add_argument("--with-mister-video-terminal", action="store_true", help="Enable Video Terminal with Mister expansion board") parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( @@ -121,7 +120,7 @@ def main(): with_mister_sdram = args.with_mister_sdram, with_mister_video_terminal = args.with_mister_video_terminal, sdram_rate = args.sdram_rate, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/de1soc.py b/litex_boards/targets/de1soc.py index 45527a2..89acd80 100755 --- a/litex_boards/targets/de1soc.py +++ b/litex_boards/targets/de1soc.py @@ -18,7 +18,6 @@ from litex_boards.platforms import de1soc from litex.soc.cores.clock import CycloneVPLL from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litedram.modules import IS42S16320 @@ -83,12 +82,12 @@ def main(): parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/de2_115.py b/litex_boards/targets/de2_115.py index f5becc4..8e65a73 100755 --- a/litex_boards/targets/de2_115.py +++ b/litex_boards/targets/de2_115.py @@ -18,7 +18,6 @@ from litex_boards.platforms import de2_115 from litex.soc.cores.clock import CycloneIVPLL from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litedram.modules import IS42S16320 @@ -83,12 +82,12 @@ def main(): parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/deca.py b/litex_boards/targets/deca.py index f5cfdb8..176efe2 100755 --- a/litex_boards/targets/deca.py +++ b/litex_boards/targets/deca.py @@ -19,7 +19,6 @@ from litex_boards.platforms import deca from litex.soc.cores.clock import Max10PLL from litex.soc.integration.soc import SoCRegion from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.video import VideoDVIPHY from litex.soc.cores.led import LedChaser @@ -83,13 +82,13 @@ def main(): parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), with_video_terminal = args.with_video_terminal, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/fpc_iii.py b/litex_boards/targets/fpc_iii.py index 93b5691..014ba5a 100755 --- a/litex_boards/targets/fpc_iii.py +++ b/litex_boards/targets/fpc_iii.py @@ -18,7 +18,6 @@ from litex.build.lattice.trellis import trellis_args, trellis_argdict from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -150,7 +149,7 @@ def main(): sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) trellis_args(parser) args = parser.parse_args() @@ -158,7 +157,7 @@ def main(): sys_clk_freq = int(float(args.sys_clk_freq)), with_ethernet = args.with_ethernet, with_etherbone = args.with_etherbone, - **soc_sdram_argdict(args)) + **soc_core_argdict(args)) if args.with_spi_sdcard: soc.add_spi_sdcard() if args.with_sdcard: diff --git a/litex_boards/targets/genesys2.py b/litex_boards/targets/genesys2.py index 69ea8b7..44f29ec 100755 --- a/litex_boards/targets/genesys2.py +++ b/litex_boards/targets/genesys2.py @@ -15,7 +15,6 @@ from litex_boards.platforms import genesys2 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -108,14 +107,14 @@ def main(): sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), with_ethernet = args.with_ethernet, with_etherbone = args.with_etherbone, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) if args.with_spi_sdcard: soc.add_spi_sdcard() diff --git a/litex_boards/targets/hadbadge.py b/litex_boards/targets/hadbadge.py index f4c8a42..b5aa61d 100755 --- a/litex_boards/targets/hadbadge.py +++ b/litex_boards/targets/hadbadge.py @@ -24,7 +24,6 @@ from litex.build.lattice.trellis import trellis_args, trellis_argdict from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litedram import modules as litedram_modules @@ -90,14 +89,14 @@ def main(): parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond") parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency (default: 48MHz)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) trellis_args(parser) args = parser.parse_args() soc = BaseSoC( toolchain = args.toolchain, sys_clk_freq = int(float(args.sys_clk_freq)), - **soc_sdram_argdict(args)) + **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} builder.build(**builder_kargs, run=args.build) diff --git a/litex_boards/targets/kc705.py b/litex_boards/targets/kc705.py index c4031b0..d2d17b9 100755 --- a/litex_boards/targets/kc705.py +++ b/litex_boards/targets/kc705.py @@ -17,7 +17,6 @@ from litex_boards.platforms import kc705 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -152,7 +151,7 @@ def main(): parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") parser.add_argument("--with-sata", action="store_true", help="Enable SATA support (over SFP2SATA)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( @@ -160,7 +159,7 @@ def main(): with_ethernet = args.with_ethernet, with_pcie = args.with_pcie, with_sata = args.with_sata, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py index ed383a6..d171314 100755 --- a/litex_boards/targets/kcu105.py +++ b/litex_boards/targets/kcu105.py @@ -16,7 +16,6 @@ from litex_boards.platforms import kcu105 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -168,7 +167,7 @@ def main(): parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") parser.add_argument("--with-sata", action="store_true", help="Enable SATA support (over SFP2SATA)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( @@ -178,7 +177,7 @@ def main(): eth_ip = args.eth_ip, with_pcie = args.with_pcie, with_sata = args.with_sata, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/kx2.py b/litex_boards/targets/kx2.py index 8b6b143..958a8af 100755 --- a/litex_boards/targets/kx2.py +++ b/litex_boards/targets/kx2.py @@ -15,7 +15,6 @@ from litex_boards.platforms import kx2 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -90,12 +89,12 @@ def main(): parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 125MHz)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/linsn_rv901t.py b/litex_boards/targets/linsn_rv901t.py index 232a984..34e980d 100755 --- a/litex_boards/targets/linsn_rv901t.py +++ b/litex_boards/targets/linsn_rv901t.py @@ -16,7 +16,6 @@ from litex.build.io import DDROutput from litex_boards.platforms import linsn_rv901t from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.clock import S6PLL from litex.soc.cores.led import LedChaser @@ -100,12 +99,12 @@ def main(): parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY: 0 (default) or 1") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/litefury.py b/litex_boards/targets/litefury.py index 794418f..d0ce977 100755 --- a/litex_boards/targets/litefury.py +++ b/litex_boards/targets/litefury.py @@ -17,7 +17,6 @@ from litex_boards.platforms import litefury from litex.soc.interconnect.csr import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.clock import * @@ -110,13 +109,13 @@ def main(): parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), with_pcie = args.with_pcie, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/logicbone.py b/litex_boards/targets/logicbone.py index 54083be..18084fa 100755 --- a/litex_boards/targets/logicbone.py +++ b/litex_boards/targets/logicbone.py @@ -18,7 +18,6 @@ from litex.build.lattice.trellis import trellis_args, trellis_argdict from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -167,7 +166,7 @@ def main(): parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) trellis_args(parser) args = parser.parse_args() @@ -177,7 +176,7 @@ def main(): sys_clk_freq = int(float(args.sys_clk_freq)), sdram_device = args.sdram_device, with_ethernet = args.with_ethernet, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) if args.with_sdcard: soc.add_sdcard() diff --git a/litex_boards/targets/mercury_xu5.py b/litex_boards/targets/mercury_xu5.py index 6317ac1..9e35d92 100755 --- a/litex_boards/targets/mercury_xu5.py +++ b/litex_boards/targets/mercury_xu5.py @@ -16,7 +16,6 @@ from litex_boards.platforms import mercury_xu5 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -98,12 +97,12 @@ def main(): parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/mimas_a7.py b/litex_boards/targets/mimas_a7.py index 31ad0fe..8268ece 100755 --- a/litex_boards/targets/mimas_a7.py +++ b/litex_boards/targets/mimas_a7.py @@ -17,7 +17,6 @@ from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -104,14 +103,14 @@ def main(): parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) vivado_build_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), with_ethernet = args.with_ethernet, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(**vivado_build_argdict(args), run=args.build) diff --git a/litex_boards/targets/minispartan6.py b/litex_boards/targets/minispartan6.py index 8230b61..bf416dd 100755 --- a/litex_boards/targets/minispartan6.py +++ b/litex_boards/targets/minispartan6.py @@ -21,7 +21,6 @@ from litex_boards.platforms import minispartan6 from litex.soc.cores.clock import S6PLL from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.video import VideoS6HDMIPHY from litex.soc.cores.led import LedChaser @@ -121,7 +120,7 @@ def main(): viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI)") viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( @@ -129,7 +128,7 @@ def main(): sdram_rate = args.sdram_rate, with_video_terminal = args.with_video_terminal, with_video_framebuffer = args.with_video_framebuffer, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/mist.py b/litex_boards/targets/mist.py index 508d204..68aeaa4 100755 --- a/litex_boards/targets/mist.py +++ b/litex_boards/targets/mist.py @@ -19,7 +19,6 @@ from litex_boards.platforms import mist from litex.soc.cores.clock import CycloneIVPLL from litex.soc.integration.soc import SoCRegion from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.video import VideoVGAPHY from litex.soc.cores.led import LedChaser @@ -100,13 +99,13 @@ def main(): parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), with_video_terminal=args.with_video_terminal, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py index 0972517..71dab2a 100755 --- a/litex_boards/targets/nereid.py +++ b/litex_boards/targets/nereid.py @@ -17,7 +17,6 @@ from litex_boards.platforms import nereid from litex.soc.interconnect.csr import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.clock import * @@ -102,13 +101,13 @@ def main(): parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), with_pcie = args.with_pcie, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/netv2.py b/litex_boards/targets/netv2.py index e53aa03..fa3921a 100755 --- a/litex_boards/targets/netv2.py +++ b/litex_boards/targets/netv2.py @@ -16,7 +16,6 @@ from litex_boards.platforms import netv2 from litex.soc.interconnect.csr import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.clock import * @@ -129,7 +128,7 @@ def main(): sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( @@ -137,7 +136,7 @@ def main(): sys_clk_freq = int(float(args.sys_clk_freq)), with_ethernet = args.with_ethernet, with_pcie = args.with_pcie, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) if args.with_spi_sdcard: soc.add_spi_sdcard() diff --git a/litex_boards/targets/nexys4ddr.py b/litex_boards/targets/nexys4ddr.py index 487e4b1..0eef966 100755 --- a/litex_boards/targets/nexys4ddr.py +++ b/litex_boards/targets/nexys4ddr.py @@ -16,7 +16,6 @@ from litex_boards.platforms import nexys4ddr from litex.soc.cores.clock import * from litex.soc.integration.soc import SoCRegion from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.video import VideoVGAPHY from litex.soc.cores.led import LedChaser @@ -126,7 +125,7 @@ def main(): viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)") viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( @@ -135,7 +134,7 @@ def main(): with_etherbone = args.with_etherbone, with_video_terminal = args.with_video_terminal, with_video_framebuffer = args.with_video_framebuffer, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) if args.with_spi_sdcard: soc.add_spi_sdcard() diff --git a/litex_boards/targets/nexys_video.py b/litex_boards/targets/nexys_video.py index 1edb084..53ebf8d 100755 --- a/litex_boards/targets/nexys_video.py +++ b/litex_boards/targets/nexys_video.py @@ -16,7 +16,6 @@ from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.video import VideoS7HDMIPHY from litex.soc.cores.led import LedChaser @@ -159,7 +158,7 @@ def main(): viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI)") viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) vivado_build_args(parser) args = parser.parse_args() @@ -170,7 +169,7 @@ def main(): with_sata = args.with_sata, with_video_terminal = args.with_video_terminal, with_video_framebuffer = args.with_video_framebuffer, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) if args.with_spi_sdcard: soc.add_spi_sdcard() diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index 49c5b86..562d854 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -20,7 +20,6 @@ from litex.build.lattice.trellis import trellis_args, trellis_argdict from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -221,7 +220,7 @@ def main(): parser.add_argument("--sdram-device", default="MT41K64M16", help="SDRAM device (default: MT41K64M16)") parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) trellis_args(parser) args = parser.parse_args() @@ -231,7 +230,7 @@ def main(): device = args.device, sdram_device = args.sdram_device, sys_clk_freq = int(float(args.sys_clk_freq)), - **soc_sdram_argdict(args)) + **soc_core_argdict(args)) if args.with_spi_sdcard: soc.add_spi_sdcard() builder = Builder(soc, **builder_argdict(args)) diff --git a/litex_boards/targets/pipistrello.py b/litex_boards/targets/pipistrello.py index 4fd01aa..9c2031b 100755 --- a/litex_boards/targets/pipistrello.py +++ b/litex_boards/targets/pipistrello.py @@ -21,7 +21,6 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex_boards.platforms import pipistrello from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -203,10 +202,10 @@ def main(): parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() - soc = BaseSoC(**soc_sdram_argdict(args)) + soc = BaseSoC(**soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/qmtech_ep4ce15.py b/litex_boards/targets/qmtech_ep4ce15.py index b7b7662..f8a4376 100755 --- a/litex_boards/targets/qmtech_ep4ce15.py +++ b/litex_boards/targets/qmtech_ep4ce15.py @@ -18,7 +18,6 @@ from litex_boards.platforms import qmtech_ep4ce15 from litex.soc.cores.clock import CycloneIVPLL from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -101,13 +100,13 @@ def main(): parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default) or 1:2 Half Rate") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), sdram_rate = args.sdram_rate, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/qmtech_wukong.py b/litex_boards/targets/qmtech_wukong.py index ccf0c0c..407e905 100755 --- a/litex_boards/targets/qmtech_wukong.py +++ b/litex_boards/targets/qmtech_wukong.py @@ -16,7 +16,6 @@ from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -107,15 +106,15 @@ def main(): parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") - ethopts = parser.add_mutually_exclusive_group() + ethopts = parser.add_mutually_exclusive_group() ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address") - sdopts = parser.add_mutually_exclusive_group() + sdopts = parser.add_mutually_exclusive_group() sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) vivado_build_args(parser) args = parser.parse_args() @@ -124,7 +123,7 @@ def main(): with_ethernet = args.with_ethernet, with_etherbone = args.with_etherbone, eth_ip = args.eth_ip, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) soc.platform.add_extension(qmtech_wukong._sdcard_pmod_io) if args.with_spi_sdcard: diff --git a/litex_boards/targets/sds1104xe.py b/litex_boards/targets/sds1104xe.py index 521d055..eb9ac38 100755 --- a/litex_boards/targets/sds1104xe.py +++ b/litex_boards/targets/sds1104xe.py @@ -28,7 +28,6 @@ from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litedram.modules import MT41K64M16 @@ -152,7 +151,7 @@ def main(): parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) vivado_build_args(parser) args = parser.parse_args() @@ -160,7 +159,7 @@ def main(): sys_clk_freq = int(float(args.sys_clk_freq)), with_etherbone = args.with_etherbone, eth_ip = args.eth_ip, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py index e819f2b..b1d7191 100755 --- a/litex_boards/targets/tagus.py +++ b/litex_boards/targets/tagus.py @@ -17,7 +17,6 @@ from litex_boards.platforms import tagus from litex.soc.interconnect.csr import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.clock import * @@ -112,13 +111,13 @@ def main(): parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), with_pcie = args.with_pcie, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index 7377402..83f5ace 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -18,7 +18,6 @@ from litex.build.lattice.trellis import trellis_args, trellis_argdict from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -166,18 +165,18 @@ def main(): parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond") parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") - sdopts = parser.add_mutually_exclusive_group() + sdopts = parser.add_mutually_exclusive_group() sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) trellis_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), with_ethernet = args.with_ethernet, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) if args.with_spi_sdcard: soc.add_spi_sdcard() diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py index bd98f4b..eeceb41 100755 --- a/litex_boards/targets/ulx3s.py +++ b/litex_boards/targets/ulx3s.py @@ -22,7 +22,6 @@ from litex.build.lattice.trellis import trellis_args, trellis_argdict from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.video import VideoECP5HDMIPHY from litex.soc.cores.led import LedChaser @@ -169,7 +168,7 @@ def main(): viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI)") viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) trellis_args(parser) args = parser.parse_args() @@ -183,7 +182,7 @@ def main(): with_video_terminal = args.with_video_terminal, with_video_framebuffer = args.with_video_framebuffer, spiflash = args.with_spiflash, - **soc_sdram_argdict(args)) + **soc_core_argdict(args)) if args.with_spi_sdcard: soc.add_spi_sdcard() if args.with_sdcard: diff --git a/litex_boards/targets/vc707.py b/litex_boards/targets/vc707.py index a08b443..352e89e 100755 --- a/litex_boards/targets/vc707.py +++ b/litex_boards/targets/vc707.py @@ -14,7 +14,6 @@ from litex_boards.platforms import vc707 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -102,13 +101,13 @@ def main(): parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), with_pcie_ = args.with_pcie, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/vcu118.py b/litex_boards/targets/vcu118.py index 8c3819d..73adf2c 100755 --- a/litex_boards/targets/vcu118.py +++ b/litex_boards/targets/vcu118.py @@ -17,7 +17,6 @@ from litex_boards.platforms import vcu118 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -99,12 +98,12 @@ def main(): parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index 7526dbc..694d436 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -19,7 +19,6 @@ from litex.build.lattice.trellis import trellis_args, trellis_argdict from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -147,7 +146,7 @@ def main(): parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address") parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY: 0 (default) or 1") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) trellis_args(parser) args = parser.parse_args() @@ -159,7 +158,7 @@ def main(): eth_ip = args.eth_ip, eth_phy = args.eth_phy, toolchain = args.toolchain, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} diff --git a/litex_boards/targets/xcu1525.py b/litex_boards/targets/xcu1525.py index 4fcb1b9..6b0215d 100755 --- a/litex_boards/targets/xcu1525.py +++ b/litex_boards/targets/xcu1525.py @@ -16,7 +16,6 @@ from litex_boards.platforms import xcu1525 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -150,7 +149,7 @@ def main(): parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") parser.add_argument("--with-sata", action="store_true", help="Enable SATA support (over SFP2SATA)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( @@ -158,7 +157,7 @@ def main(): ddram_channel = int(args.ddram_channel, 0), with_pcie = args.with_pcie, with_sata = args.with_sata, - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/zcu104.py b/litex_boards/targets/zcu104.py index a45d90c..c152f60 100755 --- a/litex_boards/targets/zcu104.py +++ b/litex_boards/targets/zcu104.py @@ -17,7 +17,6 @@ from litex_boards.platforms import zcu104 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser from litex.soc.cores.bitbang import I2CMaster @@ -100,12 +99,12 @@ def main(): parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), - **soc_sdram_argdict(args) + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/ztex213.py b/litex_boards/targets/ztex213.py index ea8a404..b3a7b3e 100755 --- a/litex_boards/targets/ztex213.py +++ b/litex_boards/targets/ztex213.py @@ -24,7 +24,6 @@ from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -111,12 +110,12 @@ def main(): parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) #soc_core_args(parser) vivado_build_args(parser) args = parser.parse_args() - soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), expansion=args.expansion, **soc_sdram_argdict(args)) + soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), expansion=args.expansion, **soc_core_argdict(args)) assert not (args.with_spi_sdcard and args.with_sdcard) if args.with_spi_sdcard: soc.add_spi_sdcard() #sbus only