From 59e8c2cd30feb0d100bd052b738b15fbfd456801 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 6 May 2020 12:27:07 +0200 Subject: [PATCH] acorn_cle_215: add .bin generation and --flash argument, working on hardware :). --- litex_boards/platforms/acorn_cle_215.py | 11 ++++++++++- litex_boards/targets/acorn_cle_215.py | 6 ++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/litex_boards/platforms/acorn_cle_215.py b/litex_boards/platforms/acorn_cle_215.py index 3e32e10..c2d0e6f 100644 --- a/litex_boards/platforms/acorn_cle_215.py +++ b/litex_boards/platforms/acorn_cle_215.py @@ -42,7 +42,7 @@ _io = [ Subsignal("rx_p", Pins("B10 B8 D11 D9")), Subsignal("rx_n", Pins("A10 A8 C11 C9")), Subsignal("tx_p", Pins("B6 B4 D5 D7")), - Subsignal("tx_n", Pins("A6 A4 C5 C7")) + Subsignal("tx_n", Pins("A6 A4 C5 C7")), ), # dram @@ -83,6 +83,15 @@ class Platform(XilinxPlatform): XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, toolchain="vivado") self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]") + self.toolchain.bitstream_commands = [ + "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", + "set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]", + "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]" + ] + self.toolchain.additional_commands = \ + ["write_cfgmem -force -format bin -interface spix4 -size 16 " + "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] + def create_programmer(self): return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a200t.bit") diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py index a2e062d..5a643a8 100755 --- a/litex_boards/targets/acorn_cle_215.py +++ b/litex_boards/targets/acorn_cle_215.py @@ -120,6 +120,7 @@ class PCIeSoC(SoCCore): bar0_size = 0x20000) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") + self.comb += platform.request("pcie_clkreq_n").eq(0) # Endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) @@ -171,6 +172,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on LiteX SoC on Acorn CLE 215+") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--flash", action="store_true", help="Flash bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() @@ -189,5 +191,9 @@ def main(): prog = soc.platform.create_programmer() prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) + if args.flash: + prog = soc.platform.create_programmer() + prog.flash(0, os.path.join(builder.gateware_dir, "top.bin")) + if __name__ == "__main__": main()