From 5a4e28d47d9edd8f8557f74ff772964b1eaf2247 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 27 Nov 2020 18:53:45 +0100 Subject: [PATCH] target/usb_acm: switch git clone to litex-hub/valentyusb repo (up to date with LiteX). --- litex_boards/targets/fomu.py | 2 +- litex_boards/targets/logicbone.py | 3 +-- litex_boards/targets/orangecrab.py | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/litex_boards/targets/fomu.py b/litex_boards/targets/fomu.py index 49dee26..a803595 100755 --- a/litex_boards/targets/fomu.py +++ b/litex_boards/targets/fomu.py @@ -84,7 +84,7 @@ class BaseSoC(SoCCore): # Serial ----------------------------------------------------------------------------------- # FIXME: do proper install of ValentyUSB. # FIXME: replace IoBuf with https://github.com/im-tomu/valentyusb/blob/master/valentyusb/usbcore/io.py#L13-L61. - os.system("git clone https://github.com/gregdavill/valentyusb -b hw_cdc_eptri") + os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri") sys.path.append("valentyusb") # SoCCore ---------------------------------------------------------------------------------- diff --git a/litex_boards/targets/logicbone.py b/litex_boards/targets/logicbone.py index d9acd10..54083be 100755 --- a/litex_boards/targets/logicbone.py +++ b/litex_boards/targets/logicbone.py @@ -9,7 +9,6 @@ import os import sys import argparse - from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer @@ -103,7 +102,7 @@ class BaseSoC(SoCCore): # Serial ----------------------------------------------------------------------------------- if kwargs["uart_name"] == "usb_acm": # FIXME: do proper install of ValentyUSB. - os.system("git clone https://github.com/gregdavill/valentyusb -b hw_cdc_eptri") + os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri") sys.path.append("valentyusb") # SoCCore ---------------------------------------------------------------------------------- diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index 24f9b46..c634e03 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -151,7 +151,7 @@ class BaseSoC(SoCCore): # Serial ----------------------------------------------------------------------------------- if kwargs["uart_name"] == "usb_acm": # FIXME: do proper install of ValentyUSB. - os.system("git clone https://github.com/gregdavill/valentyusb -b hw_cdc_eptri") + os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri") sys.path.append("valentyusb") else: platform.add_extension(orangecrab.feather_serial)