diff --git a/litex_boards/platforms/alveo_u280.py b/litex_boards/platforms/alveo_u280.py new file mode 100644 index 0000000..25dc6de --- /dev/null +++ b/litex_boards/platforms/alveo_u280.py @@ -0,0 +1,179 @@ +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2020 David Shah +# Copyright (c) 2020 Florent Kermarrec +# Modified for Alveo U280 by Sergiu Mosanu based on XCU1525 +# SPDX-License-Identifier: BSD-2-Clause + +from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc +from litex.build.xilinx import XilinxPlatform, VivadoProgrammer + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + # Clk / Rst + ("sysclk", 0, + Subsignal("n", Pins("BJ44"), IOStandard("LVDS")), + Subsignal("p", Pins("BJ43"), IOStandard("LVDS")), + ), + ("sysclk", 1, + Subsignal("n", Pins("BJ6"), IOStandard("LVDS")), + Subsignal("p", Pins("BH6"), IOStandard("LVDS")), + ), + ("cpu_reset", 0, Pins("L30"), IOStandard("LVCMOS18")), + + # Leds + ("user_led", 0, Pins("C32"), IOStandard("LVCMOS18")), + ("user_led", 1, Pins("D32"), IOStandard("LVCMOS18")), + ("user_led", 2, Pins("D31"), IOStandard("LVCMOS18")), + + # Serial + ("serial", 0, + Subsignal("rx", Pins("A28"), IOStandard("LVCMOS18")), + Subsignal("tx", Pins("B33"), IOStandard("LVCMOS18")), + ), + + # # PCIe + # ("pcie_x2", 0, + # Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")), + # Subsignal("clk_n", Pins("AM10")), + # Subsignal("clk_p", Pins("AM11")), + # Subsignal("rx_n", Pins("AF1 AG3")), + # Subsignal("rx_p", Pins("AF2 AG4")), + # Subsignal("tx_n", Pins("AF6 AG8")), + # Subsignal("tx_p", Pins("AF7 AG9")), + # ), + # ("pcie_x4", 0, + # Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")), + # Subsignal("clk_n", Pins("AM10")), + # Subsignal("clk_p", Pins("AM11")), + # Subsignal("rx_n", Pins("AF1 AG3 AH1 AJ3")), + # Subsignal("rx_p", Pins("AF2 AG4 AH2 AJ4")), + # Subsignal("tx_n", Pins("AF6 AG8 AH6 AJ8")), + # Subsignal("tx_p", Pins("AF7 AG9 AH7 AJ9")), + # ), + # ("pcie_x8", 0, + # Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")), + # Subsignal("clk_n", Pins("AM10")), + # Subsignal("clk_p", Pins("AM11")), + # Subsignal("rx_n", Pins("AF1 AG3 AH1 AJ3 AK1 AL3 AM1 AN3")), + # Subsignal("rx_p", Pins("AF2 AG4 AH2 AJ4 AK2 AL4 AM2 AN4")), + # Subsignal("tx_n", Pins("AF6 AG8 AH6 AJ8 AK6 AL8 AM6 AN8")), + # Subsignal("tx_p", Pins("AF7 AG9 AH7 AJ9 AK7 AL9 AM7 AN9")), + # ), + # ("pcie_x16", 0, + # Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")), + # Subsignal("clk_n", Pins("AM10")), + # Subsignal("clk_p", Pins("AM11")), + # Subsignal("rx_n", Pins("AF1 AG3 AH1 AJ3 AK1 AL3 AM1 AN3 AP1 AR3 AT1 AU3 AV1 AW3 BA1 BC1")), + # Subsignal("rx_p", Pins("AF2 AG4 AH2 AJ4 AK2 AL4 AM2 AN4 AP2 AR4 AT2 AU4 AV2 AW4 BA2 BC2")), + # Subsignal("tx_n", Pins("AF6 AG8 AH6 AJ8 AK6 AL8 AM6 AN8 AP6 AR8 AT6 AU8 AV6 BB4 BD4 BF4")), + # Subsignal("tx_p", Pins("AF7 AG9 AH7 AJ9 AK7 AL9 AM7 AN9 AP7 AR9 AT7 AU9 AV7 BB5 BD5 BF5")), + # ), + + # DDR4 SDRAM + ("ddram", 0, + Subsignal("a", Pins( + "BF46 BG43 BK45 BF42 BL45 BF43 BG42 BL43", + "BK43 BM42 BG45 BD41 BL42 BE44"), #"BE43 BL46 BH44" + IOStandard("SSTL12_DCI")), + Subsignal("act_n", Pins("BH41"), IOStandard("SSTL12_DCI")), + Subsignal("ba", Pins("BH45 BM47"), IOStandard("SSTL12_DCI")), + Subsignal("bg", Pins("BF41 BE41"), IOStandard("SSTL12_DCI")), + Subsignal("ras_n", Pins("BH44"), IOStandard("SSTL12_DCI")), # A16 + Subsignal("cas_n", Pins("BL46"), IOStandard("SSTL12_DCI")), # A15 + Subsignal("we_n", Pins("BE43"), IOStandard("SSTL12_DCI")), # A14 + Subsignal("cke", Pins("BH42"), IOStandard("SSTL12_DCI")), + Subsignal("clk_n", Pins("BJ46"), IOStandard("DIFF_SSTL12_DCI")), + Subsignal("clk_p", Pins("BH46"), IOStandard("DIFF_SSTL12_DCI")), + Subsignal("cs_n", Pins("BK46"), IOStandard("SSTL12_DCI")), + Subsignal("dq", Pins( + "BN32 BP32 BL30 BM30 BP29 BP28 BP31 BN31", + "BJ31 BH31 BF32 BF33 BH29 BH30 BF31 BG32", + "BK31 BL31 BK33 BL33 BL32 BM33 BN34 BP34", + "BH34 BH35 BF35 BF36 BJ33 BJ34 BG34 BG35", + "BM52 BL53 BL52 BL51 BN50 BN51 BN49 BM48", + "BE50 BE49 BE51 BD51 BF52 BF51 BG50 BF50", + "BH50 BJ51 BH51 BH49 BK50 BK51 BJ49 BJ48", + "BN44 BN45 BM44 BM45 BP43 BP44 BN47 BP47"), + IOStandard("POD12_DCI"), + # Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), + Misc("PRE_EMPHASIS=RDRV_240"), + Misc("EQUALIZATION=EQ_LEVEL2")), + Subsignal("dqs_n", Pins( + "BN30 BM29 BK30 BG30 BM35 BN35 BK35 BJ32", + "BM50 BP49 BF48 BG49 BJ47 BK49 BP46 BP42"), #"BJ54 BJ53" + IOStandard("DIFF_POD12"), + # Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), + Misc("PRE_EMPHASIS=RDRV_240"), + Misc("EQUALIZATION=EQ_LEVEL2")), + Subsignal("dqs_p", Pins( + "BN29 BM28 BJ29 BG29 BL35 BM34 BK34 BH32", + "BM49 BP48 BF47 BG48 BH47 BK48 BN46 BN42"), #"BH54 BJ52" + IOStandard("DIFF_POD12"), + # Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), + Misc("PRE_EMPHASIS=RDRV_240"), + Misc("EQUALIZATION=EQ_LEVEL2")), + Subsignal("odt", Pins("BG44"), IOStandard("SSTL12_DCI")), + Subsignal("reset_n", Pins("BG33"), IOStandard("LVCMOS12")), + Misc("SLEW=FAST") + ), + +] + +# Connectors --------------------------------------------------------------------------------------- + +_connectors = [] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(XilinxPlatform): + default_clk_name = "sysclk" + default_clk_period = 1e9/100e6 + + def __init__(self): + XilinxPlatform.__init__(self, "xcu280-fsvh2892-2L-e-es1", _io, _connectors, toolchain="vivado") + + def create_programmer(self): + return VivadoProgrammer() + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("sysclk", 0, loose=True), 1e9/100e6) + self.add_period_constraint(self.lookup_request("sysclk", 1, loose=True), 1e9/100e6) + # For passively cooled boards, overheating is a significant risk if airflow isn't sufficient + self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]") + # Reduce programming time + self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]") + # Other suggested configurations + self.add_platform_command("set_property CONFIG_VOLTAGE 1.8 [current_design]") + self.add_platform_command("set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]") + self.add_platform_command("set_property CONFIG_MODE SPIx4 [current_design]") + self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]") + self.add_platform_command("set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]") + self.add_platform_command("set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design]") + self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]") + self.add_platform_command("set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]") + self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design]") + # ------------------------------------------------------------------------ + # # DDR4 memory channel C0 Clock constraint / Internal Vref + # self.add_period_constraint(self.lookup_request("clk300", 0, loose=True), 1e9/300e6) + # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 40]") + # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 41]") + # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 42]") + # # DDR4 memory channel C1 Clock constraint / Internal Vref + # self.add_period_constraint(self.lookup_request("clk300", 1, loose=True), 1e9/300e6) + # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 65]") + # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]") + # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 67]") + # # DDR4 memory channel C2 Clock constraint / Internal Vref + # self.add_period_constraint(self.lookup_request("clk300", 2, loose=True), 1e9/300e6) + # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 46]") + # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 47]") + # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 48]") + # # DDR4 memory channel C3 Clock constraint / Internal Vref + # self.add_period_constraint(self.lookup_request("clk300", 3, loose=True), 1e9/300e6) + # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 70]") + # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 71]") + # self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 72]") diff --git a/litex_boards/targets/alveo_u280.py b/litex_boards/targets/alveo_u280.py new file mode 100755 index 0000000..13c15ac --- /dev/null +++ b/litex_boards/targets/alveo_u280.py @@ -0,0 +1,145 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2020 Florent Kermarrec +# Modified for Alveo U280 by Sergiu Mosanu based on XCU1525 +# SPDX-License-Identifier: BSD-2-Clause + +import os +import argparse + +from migen import * +from migen.genlib.resetsync import AsyncResetSynchronizer + +from litex_boards.platforms import alveo_u280 + +from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * +from litex.soc.integration.soc_sdram import * +from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser + +from litedram.modules import MTA18ASF2G72PZ +from litedram.phy import usddrphy + +from litepcie.phy.usppciephy import USPPCIEPHY +from litepcie.software import generate_litepcie_software + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(Module): + def __init__(self, platform, sys_clk_freq, ddram_channel): + self.rst = Signal() + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) + self.clock_domains.cd_idelay = ClockDomain() + + # # # + + self.submodules.pll = pll = USMMCM(speedgrade=-2) + self.comb += pll.reset.eq(self.rst) + #pll.register_clkin(platform.request("clk300", ddram_channel), 300e6) + pll.register_clkin(platform.request("sysclk", ddram_channel), 100e6) + pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) + pll.create_clkout(self.cd_idelay, 500e6, with_reset=False) + platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. + + self.specials += [ + Instance("BUFGCE_DIV", name="main_bufgce_div", + p_BUFGCE_DIVIDE=4, + i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), + Instance("BUFGCE", name="main_bufgce", + i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), + AsyncResetSynchronizer(self.cd_idelay, ~pll.locked), + ] + + self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys) + +# BaseSoC ------------------------------------------------------------------------------------------ + +class BaseSoC(SoCCore): + def __init__(self, sys_clk_freq=int(125e6), ddram_channel=0, with_pcie=False, **kwargs): + platform = alveo_u280.Platform() + + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on AlveoU280", + ident_version = True, + **kwargs) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, sys_clk_freq, ddram_channel) + + # DDR4 SDRAM ------------------------------------------------------------------------------- + if not self.integrated_main_ram_size: + self.submodules.ddrphy = usddrphy.USPDDRPHY( + pads = platform.request("ddram", ddram_channel), + memtype = "DDR4", + sys_clk_freq = sys_clk_freq, + iodelay_clk_freq = 500e6, + is_rdimm = True) + self.add_csr("ddrphy") + self.add_sdram("sdram", + phy = self.ddrphy, + module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) + # Workadound for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions. + platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]") + + # Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------ + self.add_ram("firmware_ram", 0x20000000, 0x8000) + + # PCIe ------------------------------------------------------------------------------------- + if with_pcie: + self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), + data_width = 128, + bar0_size = 0x20000) + self.add_csr("pcie_phy") + self.add_pcie(phy=self.pcie_phy, ndmas=1) + + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) + self.add_csr("leds") + +# Build -------------------------------------------------------------------------------------------- + +def main(): + parser = argparse.ArgumentParser(description="LiteX SoC on AlveoU280") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") + parser.add_argument("--ddram-channel", default="0", help="DDRAM channel (default: 0)") + parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") + parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") + builder_args(parser) + soc_sdram_args(parser) + args = parser.parse_args() + + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + ddram_channel = int(args.ddram_channel, 0), + with_pcie = args.with_pcie, + **soc_sdram_argdict(args) + ) + builder = Builder(soc, **builder_argdict(args)) + builder.build(run=args.build) + + if args.driver: + generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver")) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) + +if __name__ == "__main__": + main()